Patent US4651190A successfully refreshed from Google Patents.
US4651190A
Expired / Lapsed
US
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Semiconductor integrated circuit
Assignee: Toshiba Corp
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Filing: 1985-10-17
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Granted: 1987-03-17
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Expires: 2005-10-17
Abstract
Abstract A semiconductor integrated circuit includes p- and n-type semiconductor areas alternately arranged in a row direction, p-channel MOS transistor blocks arranged in each of the p-type semiconductor areas and each including two p-channel MOS transistors, n-channel MOS transistor blocks arranged in each of the n-type semiconductor areas and each including two n-channel MOS transistors, and p- and n-type diffusion areas formed, respectively, in each of the p-type semiconductor areas and in each of the n-type semiconductor areas. The MOS transistor blocks are arranged on two columns in each of the p- and n-type semiconductor areas, and each of the diffusion areas is formed in a position defined by the gate electrodes of four MOS transistors of the same channel type in the two MOS transistor blocks adjacent to each other in a row direction.
Inventors
- 👤 Hiroaki Suzuki
- 👤 Teruo Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:36
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
212 words
A semiconductor integrated circuit comprising: a plurality of p- and n-type semiconductor areas alternately arranged in a row direction; a plurality of columns of p-channel MOS transistors formed in each of said n-type semiconductor areas, said p-channel MOS transistors in each of said columns having current paths which are serially connected and having gate electrodes which are independently formed to extend in parallel in a row direction; a plurality of columns of n-channel MOS transistors formed in each of said p-type semiconductor areas, said n-channel MOS transistors in each of said columns having current paths which are serially connected and having gate electrodes which are independently formed to extend in parallel in a row direction; a plurality of n-type regions arranged on the same column, each of said n-type regions being formed in a position surrounded by the gate electrodes of two p-channel MOS transistors in each of two of said p-channel MOS transistor columns adjacent to each other in a row direction; and a plurality of p-type regions arranged in the same column, each of said p-type regions being formed in a position surrounded by the gate electrodes of two n-channel MOS transistors in each of two of said n-channel MOS transistor columns adjacent to each other in a row direction.
Claim 2
Dependent Claim
212 words
A semiconductor integrated circuit comprising: a plurality of p- and n-type semiconductor areas alternately arranged in a row direction; a plurality of columns of p-channel MOS transistors formed in each of said n-type semiconductor areas, said p-channel MOS transistors in each of said columns having current paths which are serially connected and having gate electrodes which are independently formed to extend in parallel in a row direction; a plurality of columns of n-channel MOS transistors formed in each of said p-type semiconductor areas, said n-channel MOS transistors in each of said columns having current paths which are serially connected and having gate electrodes which are independently formed to extend in parallel in a row direction; a plurality of n-type regions arranged on the same column, each of said n-type regions being formed in a position surrounded by the gate electrodes of two p-channel MOS transistors in each of two of said p-channel MOS transistor columns adjacent to each other in a row direction; and a plurality of p-type regions arranged in the same column, each of said p-type regions being formed in a position surrounded by the gate electrodes of two n-channel MOS transistors in each of two of said n-channel MOS transistor columns adjacent to each other in a row direction.
Claim 3
Dependent Claim
27 words
A semiconductor integrated circuit according to claim 1, wherein the number of the MOS transistors in each of said p- and n-channel MOS transistor columns is 2.
Claim 4
Dependent Claim
21 words
A semiconductor integrated circuit according to claim 2, wherein each of said MOS transistor columns comprises two adjacent columns of transistors.
Claim 5
Dependent Claim
28 words
A semiconductor integrated circuit according to claim 3, wherein each of said MOS transistors is formed to have a current path whose width is equal to four grids.
Claim 6
Dependent Claim
28 words
A semiconductor integrated circuit according to claim 2, wherein each of said MOS transistors is formed to have a current path whose width is equal to four grids.
Claim 7
Dependent Claim
28 words
A semiconductor integrated circuit according to claim 1, wherein each of said MOS transistors is formed to have a current path whose width is equal to four grids.
Claim 8
Dependent Claim
21 words
A semiconductor integrated circuit according to claim 1, wherein each of said MOS transistor columns comprises two adjacent columns of transistors.
References Cited (Backward Citations)
US4288804A
Cited
US4516312A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-16 | 1990-09-15 | 1991-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-16 | 1994-09-15 | 1995-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-16 | 1998-09-15 | 1999-03-17 | $7700.00 | Window Closed / Lapsed |