US4649549A — Apparatus for synchronizing linear PN sequences

Claim 1

Independent Claim 209 words

Apparatus for synchronizing the linear PN sequences contained in the heavy noise background of a receiver data-carrying spread spectrum signal, comprising (a) demodulator means (106, 109) for separating from the received signal the noisy wideband PN spread spectrum component, and for generating a chip rate clock signal; (b) resident PN generator means (110) responsive to said chip rate clock signal for producing a replica of the PN sequence with arbitrary phase; (c) running matrix inverse means (112) for obtaining the inverse (R -1 ) of the matrix (R) that is formed by n successive observations of the register of the resident generator; (d) matrix vector product means (118) for multiplying the running inverse by a column vector of noisy chips, thereby to obtain a plurality of estimates of the phase vector; (e) means (122) for smoothing and averaging the phase vector estimates, thereby to produce the smoothed phase vector (c j ); (f) dot product means (114) responsive to said smoothed phase vector and to the contents of the resident shift register for producing the properly phased PN sequence; and (g) despreading means (108) for combining the noisy chips with the properly phased PN sequence, whereby the narrowband digital data carried by the spread spectrum signal may be recovered.

Claim 2

Dependent Claim 209 words

Apparatus for synchronizing the linear PN sequences contained in the heavy noise background of a receiver data-carrying spread spectrum signal, comprising (a) demodulator means (106, 109) for separating from the received signal the noisy wideband PN spread spectrum component, and for generating a chip rate clock signal; (b) resident PN generator means (110) responsive to said chip rate clock signal for producing a replica of the PN sequence with arbitrary phase; (c) running matrix inverse means (112) for obtaining the inverse (R -1 ) of the matrix (R) that is formed by n successive observations of the register of the resident generator; (d) matrix vector product means (118) for multiplying the running inverse by a column vector of noisy chips, thereby to obtain a plurality of estimates of the phase vector; (e) means (122) for smoothing and averaging the phase vector estimates, thereby to produce the smoothed phase vector (c j ); (f) dot product means (114) responsive to said smoothed phase vector and to the contents of the resident shift register for producing the properly phased PN sequence; and (g) despreading means (108) for combining the noisy chips with the properly phased PN sequence, whereby the narrowband digital data carried by the spread spectrum signal may be recovered.

Claim 3

Dependent Claim 28 words

Apparatus as defined in claim 1, and further including phase delay computer means (130) for converting the smoothed phase vector to actual phase delay, thereby affording range computation.

Claim 4

Dependent Claim 115 words

Apparatus as defined in claim 1, wherein said matrix vector product means includes (1) a plurality of AND gates having output terminals, first input terminals [d 1 . . . d n ] receiving the data signals, and second input terminals connected with corresponding D stages of the running matrix inverse (R ij , where j=1 through n, i=1 through n); (2) a plurality of mod 2 adders connected with the output terminals of a plurality of said AND gates, respectively, thereby to provide a plurality of phase vector estimates, respectively; (3) means for smoothing the individual components of the phase vector; and (4) threshold means for deciding polarity of the individual phase vector components.

Claim 5

Dependent Claim 14 words

Apparatus as defined in claim 3, wherein said smoothing means comprises an up/down counter.

Claim 6

Dependent Claim 31 words

Apparatus as defined in claim 3, wherein said smoothing means comprises an up/down accumulator, and zero counter means for determining the amount by which the up/down accumulator is incremented or decremented.

Claim 7

Dependent Claim 238 words

Apparatus as defined in claim 1, wherein said resident PN generator means (110) includes a shift register (4), and recursion means connected with said shift register for producing the next bit depending on the n prior bits, said recursion means having a plurality of known coefficients of recursion (X 1 . . . X n-1 ); and further wherein said running matrix inverse means includes a plurality of columns i (where i=1 . . . m) each including (1) a plurality of D stage registers (14); (2) a plurality of mod 2 adders (12) connected between said registers, respectively; (3) a plurality of AND gates (10) having outputs connected with said mod 2 adders, respectively, each of said AND gates having a pair of input terminals; (4) means for applying said known coefficients of recursion (X 1 . . . X n-1 ) to one input terminal of said AND gates, respectively; (5) means for applying to the other input terminal of each of said AND gates a feedback signal provided by a connection between the output of the last D stage and the input of the first D stage of said column; and (6) means for loading in parallel to the D stages of each column, respectively, second signals (Y li . . . Y ni ) that are known a' priori functions of said coefficients of recursion, thereby loading the initial inverse (R o -1 ).

Claim 8

Dependent Claim 15 words

Apparatus as defined in claim 6, wherein the initial inverse matrix has the form ##EQU61##

Claim 9

Dependent Claim 239 words

Apparatus as defined in claim 1, wherein said resident PN generator means includes (1) a plurality of D stage registers (314); (2) a plurality of mod 2 adders (312) connected between said registers, respectively; (3) a plurality of AND gates (310) having outputs connected with said mod 2 adders, respectively, each of said AND gates having a pair of input terminals; (4) means for applying said known coefficients of recursion (X 1 . . . X n-1 ) to one input terminal of said AND gates, respectively; and (5) means for applying to the other input terminal of each of said AND gates a feedback signal provided by a connection between the output of the last D stage and the input of the first D stage of said column; and further wherein said running matrix inverse means includes a plurality of columns i (where i=1 . . . m) each including (1) a shift register (304), and recursion means connected with said shift register for producing the next bit depending on the n prior bits, said recursion means having a plurality of known coefficients of recursion (X 1 . . . X n-1 ); and (2) means for loading in parallel to the D stages of each column, respectively, second signals (Y 1i . . . Y ni ) that are known a' priori functions of said coefficients of recursion, thereby loading the initial inverse (R o -1 ).

Claim 10

Dependent Claim 190 words

Apparatus as defined in claim 1, wherein said running matrix inverse means (112) includes a plurality of rows i (where i=1 . . . m), each of said rows including (1) a plurality of D stage registers (404); (2) a plurality of mod 2 adders (412) connected between said registers, respectively; (3) a plurality of AND gates (410) having outputs connected with said mod 2 adders, respectively, each of said AND gates having a pair of input terminals; (4) means for applying said known coefficients of recursion (X 1 . . . X n-1 ) to one input terminal of said AND gates, respectively; (5) means for applying to the other input terminal of each of said AND gates a feedback signal providing by a connection between the output of the last D stage and the input of the first D stage of said row; and (6) means for loading in parallel to the D stages of each row, respectively, second signals (Y i1 . . . Y in ) that are known a' priori functions of said coefficients of recursion, thereby loading the initial inverse (R o -1 ).

Claim 11

Dependent Claim 42 words

Apparatus as defined in claim 5, wherein said zero counter means is operable to count also the number and weight of soft decisions which are used in each matrix vector dot product, thereby to obtain a more accurate up-date of the accumulation.

Claim 12

Independent Claim 190 words

The method for synchronizing the linear PN sequences contained in the heavy noise background of a received data-carrying spread spectrum signal, comprising the steps of (a) demodulating the received signal to separate therefrom the noisy widebank PN spread spectrum component and to generate a chip rate clock signal; (b) producing by resident PN generator means in response to the chip rate signal a replica of the PN sequence with arbitrary phase; (c) obtaining the running matrix inverse (R o -1 ) of the matrix (R) that is formed by n successive observations of the shift register of the resident PN generator means; (d) multiplying the running inverse by a column vector of noisy chips, thereby to obtain a plurality of estimates of the phase vector; (e) smoothing and averaging the phase vector estimates to produce the smoothed phase vector (c j ); (f) producing from the smoothed phase vector and the contents of the resident generator shift register a properly phased PN sequence; and (g) combining the noisy chips with the properly phased PN sequence, thereby to permit recovery of the narrowband digital data carried by the spread spectrum signal.

Claim 13

Independent Claim 190 words

The method for synchronizing the linear PN sequences contained in the heavy noise background of a received data-carrying spread spectrum signal, comprising the steps of (a) demodulating the received signal to separate therefrom the noisy widebank PN spread spectrum component and to generate a chip rate clock signal; (b) producing by resident PN generator means in response to the chip rate signal a replica of the PN sequence with arbitrary phase; (c) obtaining the running matrix inverse (R o -1 ) of the matrix (R) that is formed by n successive observations of the shift register of the resident PN generator means; (d) multiplying the running inverse by a column vector of noisy chips, thereby to obtain a plurality of estimates of the phase vector; (e) smoothing and averaging the phase vector estimates to produce the smoothed phase vector (c j ); (f) producing from the smoothed phase vector and the contents of the resident generator shift register a properly phased PN sequence; and (g) combining the noisy chips with the properly phased PN sequence, thereby to permit recovery of the narrowband digital data carried by the spread spectrum signal.

Claim 14

Dependent Claim 27 words

The method as defined in claim 11, and further including the step of delaying the phase of the smoothed averaged phase vector for use in range computation.

Claim 15

Dependent Claim 41 words

The method as defined in claim 12, and further including the step of combining phase-advanced adn phase-retarded versions of the properly phased PN sequence to produce a combined control signal (V 1 -V 2 ) for synchronizing the chip rate clock.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1990-03-09	1990-09-08	1991-03-10	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1994-03-09	1994-09-08	1995-03-10	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1998-03-09	1998-09-08	1999-03-10	$7700.00	Window Closed / Lapsed

Apparatus for synchronizing linear PN sequences

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