Up-to-speed enable for jam under load and phase loss

Claim 2

A motor controller, comprising: means for detecting a motor current; means responsive to said motor current for generating a first signal as said motor current rises through a first predetermined value as a result of an initial current rise when electric power is first switched on to said motor; means responsive to said motor current for generating a second signal as said motor current falls through a second predetermined value after said initial current rise, said second predetermined value being less than said first predetermined value; and, means responsive to both said first signal and said second signal for generating an up-to-speed enable signal so that said up-to-speed enable signal is generated after the motor current rises through said first predetermined value and subsequently falls through said second predetermined value.

Claim 3

A motor controller as in claim 1 further comprising; means for detecting a fault condition; means, responsive to both said up-to-speed enable signal and said means for detecting a fault condition, for disconnecting electric power from said motor when both said up-to-speed enable signal is present and a fault condition is detected.

Claim 4

A motor controller as in claim 2 wherein said fault condition is an over current condition.

Claim 5

A motor controller as in claim 2 wherein said fault condition is an under current condition.

Claim 6

A motor controller as in claim 2 wherein said fault condition is a phase loss condition.

Claim 7

A motor controller as in claim 1 wherein said first predetermined value is approximately 200% of the motor rated full load current.

Claim 8

A motor controller as in claim 1 wherein said second predetermined level is approximately 115% of the motor rated full load current.

Claim 9

A motor controller which generates a signal showing that the motor has reached an up-to-speed condition during a start, comprising: means for generating a voltage proportional to a motor current; means responsive to said motor current for generating a first signal as said motor current rises through a first predetermined value as a result of an initial current rise when electric power is first switched on to said motor having, a first operational amplifier (192) having a first input connected to a voltage reference and a second input connected to said voltage proportional to said motor current so that the output of said first operational amplifier (192) changes state as said motor current rises past said first predetermined value; means responsive to said motor current for generating a second signal as said motor current falls through a second predetermined value after said initial current rise, said second predetermined value being less than said first predetermined value having, a second operational amplifier (190) having a first terminal connected to a voltage reference and a second terminal connected to said voltage proportional to said motor current so that the output of said second operational amplifier (190) changes state as said motor current falls from a value exceeding said second predetermined value to a smaller value; means responsive to both said first signal and said second signal for generating an up-to-speed enable signal so that said up-to-speed enable signal is generated after the motor current rises through said first predetermined value and subsequently falls through said second predetermined value having, a first bistable flip flop (198) having a first input connected to said first operational amplifier (192) and having a second input connected to said second operational amplifier (190); a second bistable flip flop (204) having a first input connected to the output of said first bistable flip flop (198); a third bistable flip flop (202) having a first input connected to the output of said first operational amplifier (192), the output of said second bistable flip flop (204) connected to a second input of said third bistable flip flop (202), and the output of said third bistable flip flop (202) connected to a second input of said second bistable flip flop (204); and, a third operational amplifier (206) having a first input connected to said output of said second bistable flip flop (204), and a second input connected to said output of said third bistable flip flop (202) so that the output voltage of said third operational amplifier provides said up-to-speed enable signal.

Claim 10

A motor controller which generates a signal showing that the motor has reached an up-to-speed condition during a start, comprising: means for generating a voltage proportional to a motor current; means responsive to said motor current for generating a first signal as said motor current rises through a first predetermined value as a result of an initial current rise when electric power is first switched on to said motor having, a first operational amplifier (192) having a first input connected to a voltage reference and a second input connected to said voltage proportional to said motor current so that the output of said first operational amplifier (192) changes state as said motor current rises past said first predetermined value; means responsive to said motor current for generating a second signal as said motor current falls through a second predetermined value after said initial current rise, said second predetermined value being less than said first predetermined value having, a second operational amplifier (190) having a first terminal connected to a voltage reference and a second terminal connected to said voltage proportional to said motor current so that the output of said second operational amplifier (190) changes state as said motor current falls from a value exceeding said second predetermined value to a smaller value; means responsive to both said first signal and said second signal for generating an up-to-speed enable signal so that said up-to-speed enable signal is generated after the motor current rises through said first predetermined value and subsequently falls through said second predetermined value having, a first bistable flip flop (198) having a first input connected to said first operational amplifier (192) and having a second input connected to said second operational amplifier (190); a second bistable flip flop (204) having a first input connected to the output of said first bistable flip flop (198); a third bistable flip flop (202) having a first input connected to the output of said first operational amplifier (192), the output of said second bistable flip flop (204) connected to a second input of said third bistable flip flop (202), and the output of said third bistable flip flop (202) connected to a second input of said second bistable flip flop (204); and, a third operational amplifier (206) having a first input connected to said output of said second bistable flip flop (204), and a second input connected to said output of said third bistable flip flop (202) so that the output voltage of said third operational amplifier provides said up-to-speed enable signal.

Claim 11

A motor controller, comprising: means for detecting a motor current; means responsive to said motor current for generating a first signal as said motor current rises through a first predetermined value as a result of an initial current rise when electric power is first switched on to said motor; means responsive to said motor current for generating a second signal as said motor current falls through a second predetermined value after said initial current rise, said second predetermined value being less than said first predetermined value; and, means responsive to both said first signal and said second signal for generating an up-to-speed enable signal so that said up-to-speed enable signal is generated after the motor current rises through said first predetermined value and subsequently falls through said second predetermined value; means for detecting a fault condition; means, responsive to both said up-to-speed enable signal and said means for detecting a fault condition, for disconnecting electric power from said motor when both said up-to-speed enable signal is present and a fault condition is detected.

Claim 12

A motor controller, comprising: means for detecting a motor current; means responsive to said motor current for generating a first signal as said motor current rises through a first predetermined value as a result of an initial current rise when electric power is first switched on to said motor; means responsive to said motor current for generating a second signal as said motor current falls through a second predetermined value after said initial current rise, said second predetermined value being less than said first predetermined value; and, means responsive to both said first signal and said second signal for generating an up-to-speed enable signal so that said up-to-speed enable signal is generated after the motor current rises through said first predetermined value and subsequently falls through said second predetermined value; means for detecting a fault condition; means, responsive to both said up-to-speed enable signal and said means for detecting a fault condition, for disconnecting electric power from said motor when both said up-to-speed enable signal is present and a fault condition is detected.

Claim 13

A motor controller which generates a signal showing that the motor has reached an up-to-speed condition during a start, comprising: a detector for motor current, said detector capable of producing a voltage proportional to said motor current; a first operational amplifier (192) having a first input connected to a first voltage reference and a second input connected to said voltage proportional to said motor current so that the output of said first operational amplifier changes state as said motor current rises past said first predetermined value; a second operational amplifier (190) having a first input connected to a second voltage reference and a second input connected to said voltage proportional to said motor current so that the output of said second operational amplifier changes state as said motor current falls from the value exceeding said second predetermined value to a smaller value; a first bistable flip flop (198) having a first input connected to said first operational amplifier (192) and having a second input connected to said second operational amplifier (190); a second bistable flip flop (204) having a first input connected to the output of said first bistable flip flop; a third bistable flip flop (202) having a first input connected to the output of said first operational amplifier (192), the output of said second bistable flip flop (204) connected to a second input of said third bistable flip flop (20), and the output of said third bistable flip flop (202) connected to a second input of said second bistable flip flop; and, a third operational amplifier (206) having a first input connected to said output of said second bistable flip flop (204), and a second input connected to said output of said third bistable flip flop (20) so that the output voltage of said third operational amplifier (206) provides an up-to-speed enable signal.

Claim 14

A motor controller which generates a signal showing that the motor has reached an up-to-speed condition during a start, comprising: a detector for motor current, said detector capable of producing a voltage proportional to said motor current; a first operational amplifier (192) having a first input connected to a first voltage reference and a second input connected to said voltage proportional to said motor current so that the output of said first operational amplifier changes state as said motor current rises past said first predetermined value; a second operational amplifier (190) having a first input connected to a second voltage reference and a second input connected to said voltage proportional to said motor current so that the output of said second operational amplifier changes state as said motor current falls from the value exceeding said second predetermined value to a smaller value; a first bistable flip flop (198) having a first input connected to said first operational amplifier (192) and having a second input connected to said second operational amplifier (190); a second bistable flip flop (204) having a first input connected to the output of said first bistable flip flop; a third bistable flip flop (202) having a first input connected to the output of said first operational amplifier (192), the output of said second bistable flip flop (204) connected to a second input of said third bistable flip flop (20), and the output of said third bistable flip flop (202) connected to a second input of said second bistable flip flop; and, a third operational amplifier (206) having a first input connected to said output of said second bistable flip flop (204), and a second input connected to said output of said third bistable flip flop (20) so that the output voltage of said third operational amplifier (206) provides an up-to-speed enable signal.