US4647800A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed logic apparatus
Assignee: Verizon Laboratories Inc
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Filing: 1985-12-09
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Granted: 1987-03-03
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Expires: 2005-12-09
Abstract
Abstract A high speed laser driver includes a differential pair of bipolar transistors sharing a common emitter resistor as in the prior art. However, an improvement thereover resides in the use of Schottky barrier diodes, one of which couples the emitter of one transistor to the common emitter resistor and the other of which couples the emitter of the other transistor to the common emitter resistor. Furthermore, separate resistors couple the emitters of both transistors to a voltage source so that the transistors are always conducting. A high speed logic circuit includes a pair of input bipolar transistors, and a reference transistor, sharing a common emitter resistor as in the prior art. However, an important resides thereover in the use of Schottky barrier diodes that couple the emitters of the transistors to the common emitter resistor. Furthermore, separate resistors couple the emitters of the three transistors to a voltage source so that the transistors are always conducting. Schottky barrier diodes are used in the emitters of ECL logic circuits, substantially increasing switching speed.
Inventors
- 👤 George J. Meslner
- 👤 Peter N. Baum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:14
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/603; H03K17/04; H03K17/041; H03K17/0416; H03K17/04166
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
295 words
In a logic circuit including a first input transistor having one electrode adapted to be coupled to a point of reference potential, a second electrode, and a control electrode adapted to receive a first input signal ranging from one voltage level to a second voltage level; a second input transistor having one electrode adapted to be coupled to said point of reference potential, a second electrode, and a control electrode adapted to receive a second input signal ranging from said one voltage level to said second voltage level; a serial circuit including an impedance and a reference transistor having one electrode coupled to said impedance, a second electrode, and a control electrode adapted to be coupled to a bias level between said one voltage level and said second voltage level; said impedance being adapted to be coupled to said point of reference potential; a first resistor having one terminal adapted to be coupled to a third voltage level, and a second terminal; first means coupling said second electrode of said first input transistor to said second terminal; second means coupling said second electrode of said second input transistor to said second terminal; and third means coupling said second electrode of said reference transistor to said second terminal, the improvement wherein said first means includes a first high speed diode, said second means includes a second high speed diode, said third means includes a third high speed diode, and wherein the improvement further comprises a second resistor for coupling said second electrode of said first transistor to said third voltage level; a third resistor for coupling said second electrode of said second transistor to said third voltage level; and a fourth resistor for coupling said second electrode of said reference transistor to said third voltage level.
Claim 2
Dependent Claim
295 words
In a logic circuit including a first input transistor having one electrode adapted to be coupled to a point of reference potential, a second electrode, and a control electrode adapted to receive a first input signal ranging from one voltage level to a second voltage level; a second input transistor having one electrode adapted to be coupled to said point of reference potential, a second electrode, and a control electrode adapted to receive a second input signal ranging from said one voltage level to said second voltage level; a serial circuit including an impedance and a reference transistor having one electrode coupled to said impedance, a second electrode, and a control electrode adapted to be coupled to a bias level between said one voltage level and said second voltage level; said impedance being adapted to be coupled to said point of reference potential; a first resistor having one terminal adapted to be coupled to a third voltage level, and a second terminal; first means coupling said second electrode of said first input transistor to said second terminal; second means coupling said second electrode of said second input transistor to said second terminal; and third means coupling said second electrode of said reference transistor to said second terminal, the improvement wherein said first means includes a first high speed diode, said second means includes a second high speed diode, said third means includes a third high speed diode, and wherein the improvement further comprises a second resistor for coupling said second electrode of said first transistor to said third voltage level; a third resistor for coupling said second electrode of said second transistor to said third voltage level; and a fourth resistor for coupling said second electrode of said reference transistor to said third voltage level.
Claim 3
Dependent Claim
28 words
The improvement as recited in claim 1 wherein said transistors are of the same conductivity type, and wherein each said high speed diode is a Schottky barrier diode.
Claim 4
Dependent Claim
137 words
The improvement as recited in claim 2 wherein all said transistors are bipolar n-p-n semiconductor transistors; said one electrode, said second electrode and said control electrode of said first transistor are collector, emitter, and base electrodes, respectively; said one electrode, said second electrode, and said control electrode of said second transistor are collector, emitter, and base electrodes, respectively; said one electrode, said second electrode, and said control electrode of said reference transistor are collector, emitter, and base electrodes, respectively, and said first high speed diode has an anode coupled to said first transistor emitter, said second high speed diode has an anode coupled to said second transistor emitter, said third high speed diode has an anode coupled to said reference transistor emitter, and each of said high speed diodes having a respective cathode coupled to each other.
Claim 5
Dependent Claim
20 words
The improvement as recited in claim 1 wherein all recited elements are monolithically formed on a semiconductor integrated circuit chip.
Claim 6
Dependent Claim
288 words
A logic circuit comprising a first n-p-n bipolar transistor having a collector adapted to be coupled to a point of reference potential, a base adapted to receive a first input signal ranging from one voltage level to a second voltage level, and an emitter; a second n-p-n bipolar transistor having a collector adapted to be coupled to said point of reference potential, a base adapted to receive a second input signal ranging from said one voltage level to said second voltage level, and an emitter; an impedance having a first lead adapted to be coupled to said point of reference potential, and a second lead; a third n-p-n bipolar transistor having a collector coupled to said second lead of said impedance, a base adapted to be coupled to a bias level between said one voltage level and said second voltage level, and an emitter; a common resistor having one terminal adapted to be coupled to a third voltage level, and a second terminal; a first Schottky barrier diode having an anode coupled to said emitter of said first transistor, and a cathode; a second Schottky barrier diode having an anode coupled to said emitter of said second transistor, and a cathode; a third Schottky barrier diode having an anode coupled to said emitter of said third transistor, and a cathode, said cathodes of all said Schottky barrier diodes being coupled together to said second terminal of said common resistor; a second resistor for coupling said emitter of said first transistor to said third voltage level; a third resistor for coupling said emitter of said second transistor to said third voltage level; and a fourth resistor for coupling said emitter of said third transistor to said third voltage level.
Claim 7
Dependent Claim
288 words
A logic circuit comprising a first n-p-n bipolar transistor having a collector adapted to be coupled to a point of reference potential, a base adapted to receive a first input signal ranging from one voltage level to a second voltage level, and an emitter; a second n-p-n bipolar transistor having a collector adapted to be coupled to said point of reference potential, a base adapted to receive a second input signal ranging from said one voltage level to said second voltage level, and an emitter; an impedance having a first lead adapted to be coupled to said point of reference potential, and a second lead; a third n-p-n bipolar transistor having a collector coupled to said second lead of said impedance, a base adapted to be coupled to a bias level between said one voltage level and said second voltage level, and an emitter; a common resistor having one terminal adapted to be coupled to a third voltage level, and a second terminal; a first Schottky barrier diode having an anode coupled to said emitter of said first transistor, and a cathode; a second Schottky barrier diode having an anode coupled to said emitter of said second transistor, and a cathode; a third Schottky barrier diode having an anode coupled to said emitter of said third transistor, and a cathode, said cathodes of all said Schottky barrier diodes being coupled together to said second terminal of said common resistor; a second resistor for coupling said emitter of said first transistor to said third voltage level; a third resistor for coupling said emitter of said second transistor to said third voltage level; and a fourth resistor for coupling said emitter of said third transistor to said third voltage level.
Claim 8
Dependent Claim
21 words
The logic circuit as recited in claim 5 wherein all recited elements are formed monolithically on an integrated semiconductor circuit chip.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-02 | 1990-09-01 | 1991-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-02 | 1994-09-01 | 1995-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-02 | 1998-09-01 | 1999-03-03 | $7700.00 | Window Closed / Lapsed |