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US4647172A Expired / Lapsed US ⏱️ 0.0 years remaining

Resist development method

Assignee: GCA Corp
•
Filing: 1985-05-17
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Granted: 1987-03-03
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Expires: 2005-05-17
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Abstract

Abstract In the resist development method disclosed herein, the spin development of a resist coating on the surface of a semiconductor wafer is monitored by measuring light scattered back from the wafer surface from an incandescent source. During development, the sensed light level oscillates due to optical fringing caused by the thinning of the resist layer in the exposed areas and the fringe generated oscillation essentially stops when the development breaks through in the exposed areas. By comparing sample data obtained from the sensed light level with template data representing a known or characteristic behavior, a control point corresonding to the last fringe may be determined. Development is then terminated a calculated time after the control point.

Inventors

  • 👤 William T. Batchelder
  • 👤 John A. Piatt
  • 👤 Kenneth M. Sautter

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 08:59
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/26; G03F7/30; G03F7/3021; G03F7/3028; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 163 words
Apparatus for developing exposed resist on the surface of a semiconductor wafer during fabrication of integrated circuits which comprises: means for spinning the wafer; means for spraying developer on the wafer surface to cause development of the resist; means illuminating at least a spot on the wafer surface from an incandescent light source; a photodetector, for sensing light scattered back from the illuminated spot on the wafer surface and generating therefrom a signal voltage; means for periodically digiting said voltage to generate sample data; means for storing reference data representing a template characteristic of a representative development process, said reference data including a reference control point which characterizes a known point in the reference development process; means for comparing the sample data and the reference data to obtain a best fit and to thereby locate a control point in the sample data which corresponds to the reference control point; and means for terminating development a calculated time interval after said sample control point.
Claim 2
Dependent Claim 163 words
Apparatus for developing exposed resist on the surface of a semiconductor wafer during fabrication of integrated circuits which comprises: means for spinning the wafer; means for spraying developer on the wafer surface to cause development of the resist; means illuminating at least a spot on the wafer surface from an incandescent light source; a photodetector, for sensing light scattered back from the illuminated spot on the wafer surface and generating therefrom a signal voltage; means for periodically digiting said voltage to generate sample data; means for storing reference data representing a template characteristic of a representative development process, said reference data including a reference control point which characterizes a known point in the reference development process; means for comparing the sample data and the reference data to obtain a best fit and to thereby locate a control point in the sample data which corresponds to the reference control point; and means for terminating development a calculated time interval after said sample control point.
Claim 3
Dependent Claim 162 words
Apparatus for developing exposed resist on the surface of a semiconductor wafer during fabrication of integrated circuits which comprises: means for spinning the wafer; means for spraying developer on the wafer surface to cause development of the resist; means illuminating at least a spot on the wafer surface; a photodetector, for sensing light scattered back from the illuminated spot on the wafer surface and generating therefrom a signal voltage; means for periodically digiting said voltage to generate sample data; means for storing reference data representing a template characteristic of optical fringes generated by a representative development process, said reference data including a reference control point which characterizes a last fringe in the reference development process; means for comparing the sample data and the reference data to obtain a best fit and to thereby locate a control point in the sample data which corresponds to the reference control point; and means for terminating development a calculated time interval after said sample control point.
Claim 4
Dependent Claim 162 words
Apparatus for developing exposed resist on the surface of a semiconductor wafer during fabrication of integrated circuits which comprises: means for spinning the wafer; means for spraying developer on the wafer surface to cause development of the resist; means illuminating at least a spot on the wafer surface; a photodetector, for sensing light scattered back from the illuminated spot on the wafer surface and generating therefrom a signal voltage; means for periodically digiting said voltage to generate sample data; means for storing reference data representing a template characteristic of optical fringes generated by a representative development process, said reference data including a reference control point which characterizes a last fringe in the reference development process; means for comparing the sample data and the reference data to obtain a best fit and to thereby locate a control point in the sample data which corresponds to the reference control point; and means for terminating development a calculated time interval after said sample control point.
Claim 5
Dependent Claim 157 words
Apparatus for developing exposed resist on the surface of a semiconductor wafer during fabrication of integrated circuits which comprises: means for spinning the wafer; means for spraying developer on the wafer surface to cause development of the resist; means illuminating at least a spot on the wafer surface during development from an incandescent light source filtered to provide only non-exposing wavelengths; a photodetector, for sensing light scattered back from the illuminated spot on the wafer surface and generating therefrom a signal voltage; means for periodically digiting said voltage to generate sample data; means for storing reference data representing a template characteristic of optical fringes generated by a representative development process, said reference data including a reference control point which means for analyzing the sample data to locate a control point in the sample data which characterizes a last fringe in the reference development process; and means for terminating development a calculated time interval after said control point.
Claim 6
Dependent Claim 157 words
Apparatus for developing exposed resist on the surface of a semiconductor wafer during fabrication of integrated circuits which comprises: means for spinning the wafer; means for spraying developer on the wafer surface to cause development of the resist; means illuminating at least a spot on the wafer surface during development from an incandescent light source filtered to provide only non-exposing wavelengths; a photodetector, for sensing light scattered back from the illuminated spot on the wafer surface and generating therefrom a signal voltage; means for periodically digiting said voltage to generate sample data; means for storing reference data representing a template characteristic of optical fringes generated by a representative development process, said reference data including a reference control point which means for analyzing the sample data to locate a control point in the sample data which characterizes a last fringe in the reference development process; and means for terminating development a calculated time interval after said control point.

References Cited (Backward Citations)

US4136940A Cited
US4469424A Cited
US4501480A Cited
US4462860A Cited
US4569717A Cited
US4493745A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-03-02 1990-09-01 1991-03-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-03-02 1994-09-01 1995-03-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-03-02 1998-09-01 1999-03-03 $7700.00 Window Closed / Lapsed

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