Blend control for low voltage stereo decoders

Claim 1

A stereo blend control circuit for producing an output level related to a d-c control, said circuit comprising: first and second transistors forming a first differential pair, said first pair having input and output terminals; third and fourth transistors forming a second differential pair, said second pair having input and output terminals; means for providing a constant tail current commonly to said first and second pairs; means for cross coupling the output terminals of said first and second pairs whereby the combined output currents equal said tail current and differential signal inputs to said pairs cancel; means for providing a common direct current bias voltage to the input terminals of both of said pairs; resistive means coupled in series with the input terminals of said first pair; control current biasing means coupled to said input terminals of said first pair whereby a current is passed through said resistive means to develop an offset bias that is a function of said control current; and means for varying said control current whereby said pairs produce cancelling outputs for zero control current and maximum output for maximum control current.