QAM modulator circuit

Claim 2

A circuit for modulating data in accordance with a predetermined modulation scheme, said circuit comprising: (a) means for inputting data at a predetermined rate; (b) means for storing and retaining said inputted data for a predetermined period; (c) memory means having first and second outputs and being coupled to said storage means, for storing multiple versions of a signal constellation, said signal constellations containing precomputed representations of every possible value of said inputted data wherein each of said multiple versions is related to each other according to a predetermined phase relationship; (d) first and second processing means coupled to said first and second outputs of said memory means, respectively, for processing said precomputed data to produce output signals, said processing means being configured to provide a predetermined impulse response in quadrature with respect to each other, chosen in accordance with a predetermined modulation scheme; and (e) means coupled to said first and second processing means for combining the output signals therefrom and providing an output signal.

Claim 3

The apparatus of claim 1 wherein said first and second processing means each comprise digital filters having a finite impulse response.

Claim 4

The apparatus of claim 1 wherein said first and second processing means each comprise surface acoustic wave filters.

Claim 5

The apparatus of claim 1 wherein said memory means further includes a binary counter coupled to an address input of said memory means for sequentially selecting particular versions of the signal constellation.

Claim 6

A circuit for modulating data in accordance with a predetermined modulation scheme, said circuit comprising: (a) A serial to parallel converter, said converter accepting serial data and providing a parallel output with a predetermined number of bits; (b) A data storage register coupled to said serial to parallel converter for retaining said parallel data for a predetermined period; (c) A signal constellation memory having first and second address inputs and first and second parallel data outputs, said first address input coupled to said data storage register, said memory containing multiple versions of a signal constellation, each of said multiple versions being related according to a predetermined phase relationship; (d) A binary counter coupled to said second address input of said signal constellation memory for sequencing said memory between each of said versions of said signal constellation; (e) A first digital filter coupled to said first parallel data output of said signal constellation memory, said first digital filter being disposed with a first predetermined impulse response; (f) A second digital filter coupled to said second parallel data output of said signal constellation memory, said second digital filter being disposed with a second predetermined impulse response; and (g) A summing network coupled to said first and second digital filter, said summing network combining the output signals of said first and second digital filters and providing an output signal.

Claim 7

A circuit for modulating data in accordance with a predetermined modulation scheme, said circuit comprising: (a) A serial to parallel converter, said converter accepting serial data and providing a parallel output with a predetermined number of bits; (b) A data storage register coupled to said serial to parallel converter for retaining said parallel data for a predetermined period; (c) A signal constellation memory having first and second address inputs and first and second parallel data outputs, said first address input coupled to said data storage register, said memory containing multiple versions of a signal constellation, each of said multiple versions being related according to a predetermined phase relationship; (d) A binary counter coupled to said second address input of said signal constellation memory for sequencing said memory between each of said versions of said signal constellation; (e) A first digital filter coupled to said first parallel data output of said signal constellation memory, said first digital filter being disposed with a first predetermined impulse response; (f) A second digital filter coupled to said second parallel data output of said signal constellation memory, said second digital filter being disposed with a second predetermined impulse response; and (g) A summing network coupled to said first and second digital filter, said summing network combining the output signals of said first and second digital filters and providing an output signal.

Claim 8

A modulator circuit for modulating data in accordance with a predetermined modulation scheme, said circuit consisting essentially of: (a) means for inputting data at a predetermined rate; (b) means for storing and retaining said data for a predetermined period; (c) memory means having a first and second parallel output, coupled to said storing means for storing precomputed values of a signal constellation, wherein said precomputed values correspond to every possible value of said captured input data; (d) first and second sampled time processing means coupled to said first and second parallel outputs of said memory means, respectively, said first and second sampled time processing means being configured to provide a predetermined impulse response chosen in accordance with a predetermined impulse response chosen in accordance with a predetermined modulation scheme and said first and second sampled time processing means having output signals disposed with quadrature relationship with respect to each other; and (e) means coupled to said first and second sampled time processing means for combining the output signals of said first and second sampled time processing means and providing an output signal.

Claim 9

A modulator circuit for modulating data in accordance with a predetermined modulation scheme, said circuit consisting essentially of: (a) means for inputting data at a predetermined rate; (b) means for storing and retaining said data for a predetermined period; (c) memory means having a first and second parallel output, coupled to said storing means for storing precomputed values of a signal constellation, wherein said precomputed values correspond to every possible value of said captured input data; (d) first and second sampled time processing means coupled to said first and second parallel outputs of said memory means, respectively, said first and second sampled time processing means being configured to provide a predetermined impulse response chosen in accordance with a predetermined impulse response chosen in accordance with a predetermined modulation scheme and said first and second sampled time processing means having output signals disposed with quadrature relationship with respect to each other; and (e) means coupled to said first and second sampled time processing means for combining the output signals of said first and second sampled time processing means and providing an output signal.

Claim 10

A circuit for modulating data in accordance with a predetermined modulation scheme, said circuit comprising: (a) a serial to parallel converter, said converter accepting serial data and providing a parallel output with a predetermined number of bits; (b) a data storage register coupled to said serial to parallel converter for retaining said parallel data for a predetermined period; (c) memory means having a first and second parallel output, coupled to said data storage means for storing precomputed values of a signal constellation, wherein said precomputed values correspond to every possible value of said captured input data; (d) a first sampled time filter coupled to said first parallel data output of said memory means, said first sampled time digital filter being disposed with a first predetermined impulse response; (e) a second sampled time filter coupled to said second parallel data output of said memory means, said second sampled time digital filter being disposed with a second predetermined impulse response; and (f) a summing network coupled to said first and second sampled time filters, said summing network combining the output signal of said first and second sampled time filters and providing an output signal.

Claim 11

A circuit for modulating data in accordance with a predetermined modulation scheme, said circuit comprising: (a) a serial to parallel converter, said converter accepting serial data and providing a parallel output with a predetermined number of bits; (b) a data storage register coupled to said serial to parallel converter for retaining said parallel data for a predetermined period; (c) memory means having a first and second parallel output, coupled to said data storage means for storing precomputed values of a signal constellation, wherein said precomputed values correspond to every possible value of said captured input data; (d) a first sampled time filter coupled to said first parallel data output of said memory means, said first sampled time digital filter being disposed with a first predetermined impulse response; (e) a second sampled time filter coupled to said second parallel data output of said memory means, said second sampled time digital filter being disposed with a second predetermined impulse response; and (f) a summing network coupled to said first and second sampled time filters, said summing network combining the output signal of said first and second sampled time filters and providing an output signal.