Self testing data processing system with system test master arbitration

Claim 2

A self testing data processing system comprising: a communications bus having a plurality of connection slots, each connection slot having a unique electrically readable slot number, said communicatins bus for bidirectional communicatins between said slots; a plurality of intelligent data processing circuits, each intelligent data processing circuit connected to one of said slots and having an identity memory means and a testing means, said identity memory means having identity data indicating said intelligent data processing circuit can be a system test master and self test data indicating whether or not said intelligent data processing circuit has passed a circuit self test, said testing means including at least one processor means for performing general data processing tasks under program control, and having a circuit testing means coupled to the identity memory means for self testing said intelligent data processing circuit and loading data into said identity memory means indicative of whether or not said intelligent data processing circuit has passed said circuit self test, a master arbitration means coupled to said communications bus for reading said identity memory means of other slots and deferring system test control if said intelligent data processing circuit has failed its circuit self test or if said identity memory means of any lower slot number has identity data indicating it can be a system test master and self test data indicating it has passed its circuit self test, and system test master means coupled to said communications bus for controlling system test if system test control is not deferred.

Claim 3

A self testing data processing system as claimed in claim 1, wherein: each intelligent data processing circuit includes means for electrically reading said unique slot number and means for generating data on said communication bus from said identity memory means in response to a read memory signal on said communicatins bus specifying an address which bears a predetermined relationship to said slot number, and wherein said master arbitration means includes means for reading said identity memory means of another slot by generating on said communications bus a read memory signal specifying an address which bears said predetermined relationship to said slot number.

Claim 4

A self testing data processing system as claimed in claim 2, wherein: said predetermined relationship of slot number to identity memory means address having the same least significant bits for each identity memory means and having the most significant bits determined by said slot number.

Claim 5

A self testing data processing system as claimed in claim 1, wherein: said identity memory means of each intelligent data processing circuit has further self test data indicating whether or not circuit self test is in progress; and said master arbitration means of each intelligent data processing circuit determines that an intelligent data processing circuit in another slot has failed its circuit self test if the self test data for that slot indicates circuit self test in progress for longer than a predetermined period of time.

Claim 6

A self testing data processing system as claimed in claim 4, wherein: said identity memory means of each intelligent data processing circuit further has test duration data indicating the test duration required to perform its circuit self test; and said master arbitration means of each intelligent data processing circuit further reads said test duration data for an intelligent data processing circuit in another slot, and further sets said predetermined period of time to be not less than said test duration.

Claim 7

A self testing data processing system as claimed in claim 1, wherein: said testing means of each intelligent data processing circuit is actuated upon initial application of electric power.

Claim 8

A self testing data processing system as claimed in claim 1, wherein: said testing means of each intelligent data processing circuit is actuated via a system reset command on said communications bus.

Claim 9

A self testing data processing system as claimed in claim 1, further comprising: at least one nonintelligent data processing circuit, each nonintelligent data processing circuit connected to one of said slots and having an identity memory means readable from said communications bus, said identity memory means having identity data indicating said nonintelligent data processing circuit cannot be a system test master; and wherein said system test master means of each intelligent data processing circuit further includes means for testing said nonintelligent data processing circuits if system test control is not deferred.

Claim 10

A self testing data processing system as claimed in claim 8, wherein: each nonintelligent data processing circuit includes means for electrically reading said unique slot number and means for generating data on said communications bus from said identity memory means in response to a read memory signal on said communications bus specifying an address which bears a predetermned relationship to said unique slot number.

Claim 11

A self testing data processing system as claimed in claim 9, wherein: said predetermined relationship of slot number to identity memory address having the same least significant bits for each identity memory means and having the most significant bits determined by said unique slot number.

Claim 12

An intelligent data processing circuit comprising: a bus connector means for connection to a communication bus for bidirectional communication, said bus connector means having slot number reading means for reading an electrically readable slot number from said communications bus; an identity memory means connected to said bus connector means for generating data on said communications bus in response to a read signal specifying an address which bears a predetermined relationship to said slot number, said data including identity data indicating that said intelligent data processing circuit can be a system test master and self test data indicating whether or not said intelligent data processing circuit has passed a circuit self test; and a testing means connected to said bus connector means for bidirectional communication with said communication bus, said testing means having at least one processor means for performing general purpose data processing tasks under program control, and including circuit testing means coupled to said identity memory means for self testing said intelligent data processing circuit and loading data into said identity memory means indicating whether or not said intelligent data processing circuit passed said circuit self test, master arbitration means coupled to said communications bus for generating on said communications bus read signals specifying addresses which bear said predetermined relationship to other slot numbers treating any response from said communications bus as identity data and self test data and deferring system test control if said intelligent data processing circuit has failed its circuit self test or if any lower slot number has identity data indicating it can be a system master and self test data indicating it can be a system master and self test data indicating it has passed its circuit self test, and a system test master means coupled to said communications bus for controlling system test via said communications bus if system test control is not deferred.

Claim 13

An intelligent data processing circuit comprising: a bus connector means for connection to a communication bus for bidirectional communication, said bus connector means having slot number reading means for reading an electrically readable slot number from said communications bus; an identity memory means connected to said bus connector means for generating data on said communications bus in response to a read signal specifying an address which bears a predetermined relationship to said slot number, said data including identity data indicating that said intelligent data processing circuit can be a system test master and self test data indicating whether or not said intelligent data processing circuit has passed a circuit self test; and a testing means connected to said bus connector means for bidirectional communication with said communication bus, said testing means having at least one processor means for performing general purpose data processing tasks under program control, and including circuit testing means coupled to said identity memory means for self testing said intelligent data processing circuit and loading data into said identity memory means indicating whether or not said intelligent data processing circuit passed said circuit self test, master arbitration means coupled to said communications bus for generating on said communications bus read signals specifying addresses which bear said predetermined relationship to other slot numbers treating any response from said communications bus as identity data and self test data and deferring system test control if said intelligent data processing circuit has failed its circuit self test or if any lower slot number has identity data indicating it can be a system master and self test data indicating it can be a system master and self test data indicating it has passed its circuit self test, and a system test master means coupled to said communications bus for controlling system test via said communications bus if system test control is not deferred.

Claim 14

An intelligent data processing circuit as claimed in claim 11, wherein: said predetermined relationship of slot number to identity memory means address having fixed least significant bits and having the most significant bits determined by said slot number.

Claim 15

An intelligent data processing circuit as claimed in claim 11, wherein: said identity memory means has further self test data indicating whether or not a circuit self test is in progress; and said master arbitration means determines that an intelligent data processing circuit in another slot has failed its circuit self test if the self test data for that slot indicates circuit self test in progress for longer than a predetermined period of time.

Claim 16

An intelligent data processing circuit as claimed in claim 11, wherein: said identity memory means further has test duration data indicating the test duration required to perform its circuit self test; and said master arbitration means reads said test duration data for an intelligent data processing in another slot, and further sets said predetermined period of time to be not less than said test duration.

Claim 17

An intelligent data processing circuit as claimed in claim 11, wherein: said testing means is actuated upon initial application of electric power.

Claim 18

An intelligent data processing circuit as claimed in claim 11, wherein: said testing means is actuated via a system reset command on said communications bus.

Claim 19

A self testing data processing system comprising: a communications bus having a plurality of connection slots, each connection slot having a unique electrically readable slot number, said communications bus for bidirectional communications between said slots; and a plurality of intelligent data processing circuits, each intelligent data processing circuit connected to one of said slots and having an identity memory means and a testing means, said identity memory means having identity data indicating said intelligent data processing circuit can be a system test master, said testing means including at least one processor means for performing general purpose data processing tasks under program control and having a master arbitration means coupled to said communications bus for reading said identity memory means of other slots and deferring system test control if said identity memory means of any lower slot number has identity data indicating it can be a system test master, and system test master means coupled to said communications bus for controlling system test if system test control is not deferred.

Claim 20

A self testing data processing system comprising: a communications bus having a plurality of connection slots, each connection slot having a unique electrically readable slot number, said communications bus for bidirectional communications between said slots; and a plurality of intelligent data processing circuits, each intelligent data processing circuit connected to one of said slots and having an identity memory means and a testing means, said identity memory means having identity data indicating said intelligent data processing circuit can be a system test master, said testing means including at least one processor means for performing general purpose data processing tasks under program control and having a master arbitration means coupled to said communications bus for reading said identity memory means of other slots and deferring system test control if said identity memory means of any lower slot number has identity data indicating it can be a system test master, and system test master means coupled to said communications bus for controlling system test if system test control is not deferred.

Claim 21

An intelligent data processing circuit comprising: a bus connector means for connection to a communicaton bus for bidirectional communication, said bus connector means having slot number reading means for reading an electrically readable slot number from said communications bus; and an identity memory means connected to said bus connector means for generating data on said communications bus in response to a read signal specifying an address which bears a predetermined relationship to said slot number, said data including identity data indicating that said intelligent data processing circuit can be a system test master; and a testing means connected to said bus connector means for bidirectional communication with said communication bus, including at least one processor means for performing general purpose data processing tasks under program control, and including master arbitration means coupled to said communications bus for generating on said communications bus read signals specifying addresses which bear predetermined relationship to other slot numbers treating any response from said communications bus as identity data and deferring system test control if any lower slot number has identity data indicating it can be system master, and a system test master means coupled to said communications bus for controlling system test via said communications bus if system test control is not deferred.

Claim 22

An intelligent data processing circuit comprising: a bus connector means for connection to a communicaton bus for bidirectional communication, said bus connector means having slot number reading means for reading an electrically readable slot number from said communications bus; and an identity memory means connected to said bus connector means for generating data on said communications bus in response to a read signal specifying an address which bears a predetermined relationship to said slot number, said data including identity data indicating that said intelligent data processing circuit can be a system test master; and a testing means connected to said bus connector means for bidirectional communication with said communication bus, including at least one processor means for performing general purpose data processing tasks under program control, and including master arbitration means coupled to said communications bus for generating on said communications bus read signals specifying addresses which bear predetermined relationship to other slot numbers treating any response from said communications bus as identity data and deferring system test control if any lower slot number has identity data indicating it can be system master, and a system test master means coupled to said communications bus for controlling system test via said communications bus if system test control is not deferred.

Claim 23

A computer system having a distributed self-test mechanism, comprising: a system bus having a plurality of slots for receiving circuit modules; at least one circuit module located in a slot which does not have the capability for self test; and at least two circuit modules which are capable of self test, and which further are capable of performing a system test, including the testing of said at least one circuit module which does not have the capability for self test; wherein said at least two circuit modules which are capable of self test each perform their individual self tests, and those which pass their self test then arbitrate among themselves to determine which circuit module will perform the system test, whereby the circuit module so selected performs the system test.

Claim 24

A computer system having a distributed self-test mechanism, comprising: a system bus having a plurality of slots for receiving circuit modules; at least one circuit module located in a slot which does not have the capability for self test; and at least two circuit modules which are capable of self test, and which further are capable of performing a system test, including the testing of said at least one circuit module which does not have the capability for self test; wherein said at least two circuit modules which are capable of self test each perform their individual self tests, and those which pass their self test then arbitrate among themselves to determine which circuit module will perform the system test, whereby the circuit module so selected performs the system test.

Claim 25

The system of claim 19, wherein all of said at least one circuit module which does not have the capability for self test and said at least two circuit modules which are capable of self test are assigned a number according to which the slots in said system bus they reside, and wherein the arbitration between said at least two circuit modules which are capable of self test selects the circuit module to perform the system test based on the slot numbers thereof.

Claim 26

The system of claim 20, wherein the circuit module having the lowest assigned slot number is selected to perform the system test.