Semiconductor bipolar memory device operating in high speed

Claim 2

A memory device comprising a plurality of memory cells, each of said memory cells including first and second transistors for holding data stored therein and first and second diodes for suppressing a lowering of potentials of said transistors, a third transistor having an emitter connected to an emitter of said first transistor, a fourth transistor having an emitter connected to an emitter of said second transistor, a first current source connected to a connection point of the emitters of said first and third transistor, a second current source connected to a connection point of the emitters of said second and fourth transistors, means for generating a first voltage having a level variation characteristic substantially equal to that of each voltage of said first and second diodes, means for providing a current based on the first voltage generated from said generating means, means for converting said current into a second voltage, and means responsive to said second voltage for supplying a third voltage to bases of said third and fourth transistors with a low output impedance, said third voltage taking an intermediate level between potentials appearing at bases of said first and second transistors, whereby one of said third and fourth transistors is made conductive in response to the data stored in a selected memory cell.

Claim 3

The memory device as claimed in claim 1, wherein said generating means includes a third diode having a junction characteristic substantially equal to that of the first and second diodes, and said supplying means includes a fifth transistor of an emitter follower type.

Claim 4

A memory device comprising a plurality of memory cells, each of said memory cells including first and second transistors for holding data stored therein and first and second diodes for suppressing a lowering of potentials of said transistors, and means for producing a reading voltage which is used for reading out the data stored in the selected memory cell, said producing means including means for generating a voltage having a level variation characteristic substantially equal to that of each voltage of said first and second diodes, means for providing a current based on the voltage generated from said generating means, means for converting said current into a voltage, and means responsive to the converted voltage for supplying said reading-out voltage with a low output impedance, said generating means including a third diode having a junction characteristic substantially equal to that of the first and second diodes, said supplying means including a third transistor of an emitter follower type, said providing means including a fourth diode, a fourth transistor and a first resistor, and said converting means including a second resistor connected in series to the collector of said fourth transistor, said fourth diode, a base-emitter junction of said fourth transistor and said first resistor cooperating with said third diode to form a closed loop circuit, said fourth diode including a p-n junction substantially equal to the base-emitter junction of said fourth transistor.

Claim 5

A memory device comprising a plurality of memory cells, each of said memory cells including first and second transistors for holding data stored therein and first and second diodes for suppressing a lowering of potentials of said transistors, and means for producing a reading voltage which is used for reading out the data stored in the selected memory cell, said producing means including means for generating a voltage having a level variation characteristic substantially equal to that of each voltage of said first and second diodes, means for providing a current based on the voltage generated from said generating means, means for converting said current into a voltage, and means responsive to the converted voltage for supplying said reading-out voltage with a low output impedance, said generating means including a third diode having a junction characteristic substantially equal to that of the first and second diodes, said supplying means including a third transistor of an emitter follower type, said providing means including a fourth diode, a fourth transistor and a first resistor, and said converting means including a second resistor connected in series to the collector of said fourth transistor, said fourth diode, a base-emitter junction of said fourth transistor and said first resistor cooperating with said third diode to form a closed loop circuit, said fourth diode including a p-n junction substantially equal to the base-emitter junction of said fourth transistor.

Claim 6

A memory device comprising at least one pair of column lines, a plurality of memory cells each including a first transistor having an emitter connected to one of said column lines and a second transistor having an emitter connected to the other of said column lines, a third transistor having an emitter connected to said one column line, a fourth transistor having an emitter connected to said other column line, a first current source connected to said one column line, a second current source connected to said other column line, a sense amplifier coupled to collectors of said third and fourth transistors, a series circuit of first and second diodes, means for biasing said first and second diodes, a fifth transistor having a base supplied with a potential at one end of said series circuit, a first resistor connected between an emitter of said fifth transistor and the other end of said series circuit, a second resistor connected to a collector of said fifth transistor, and a sixth transistor having a base supplied with a potential at the collector of said third transistor and means for connecting an emitter of said sixth transistor to bases of said third and fourth transistors.

Claim 7

A memory device comprising at least one pair of column lines, a plurality of memory cells each including a first transistor having an emitter connected to one of said column lines and a second transistor having an emitter connected to the other of said column lines, a third transistor having an emitter connected to said one column line, a fourth transistor having an emitter connected to said other column line, a first current source connected to said one column line, a second current source connected to said other column line, a sense amplifier coupled to collectors of said third and fourth transistors, a series circuit of first and second diodes, means for biasing said first and second diodes, a fifth transistor having a base supplied with a potential at one end of said series circuit, a first resistor connected between an emitter of said fifth transistor and the other end of said series circuit, a second resistor connected to a collector of said fifth transistor, and a sixth transistor having a base supplied with a potential at the collector of said third transistor and means for connecting an emitter of said sixth transistor to bases of said third and fourth transistors.

Claim 8

The memory device as claimed in claim 4, further comprising a third resistor connected in parallel to said second diode.

Claim 9

A memory device comprising a plurality of memory cells each including first and second transistors forming a flip-flop circuit, a first parallel circuit of a first resistor and a first diode provided as a load of said first transistor, and a second parallel circuit of a second resistor and a second diode provided as a load of said second transistor, a third transistor having an emitter connected to an emitter of said first transistor to form an emitter-coupled logic, a fourth transistor having an emitter connected to an emitter of said second transistor to form an emitter-coupled logic, and a read/write control circuit including a voltage producing section producing a voltage supplied to said third and fourth transistors, said voltage producing section including a fifth transistor of an emitter-follower type supplying said voltage to said third and fourth transistors with a low output impedance, said voltage taking an intermediate level between potentials appearing at bases of said first and second transistors, whereby one of said third and fourth transistors is turned ON in response to data stored in a selected memory cell.

Claim 10

A memory device comprising a plurality of memory cells each including first and second transistors forming a flip-flop circuit, a first parallel circuit of a first resistor and a first diode provided as a load of said first transistor, and a second parallel circuit of a second resistor and a second diode provided as a load of said second transistor, a third transistor having an emitter connected to an emitter of said first transistor to form an emitter-coupled logic, a fourth transistor having an emitter connected to an emitter of said second transistor to form an emitter-coupled logic, and a read/write control circuit including a voltage producing section producing a voltage supplied to said third and fourth transistors, said voltage producing section including a fifth transistor of an emitter-follower type supplying said voltage to said third and fourth transistors with a low output impedance, said voltage taking an intermediate level between potentials appearing at bases of said first and second transistors, whereby one of said third and fourth transistors is turned ON in response to data stored in a selected memory cell.

Claim 11

The memory device as claimed in claim 6 further comprising a sense amplifier coupled to collectors of said third and fourth transistors and producing output data.

Claim 12

A memory device comprising a plurality of memory cells each including first and second transistors forming a flip-flop circuit, a first parallel circuit of a first resistor and a first diode provided as a load of said first transistor, and a second parallel circuit of a second resistor and a second diode provided as a load of said second transistor, a third transistor cooperating with said first transistor to form an emitter-coupled logic, a fourth transistor cooperating with said second transistor to form an emitter-coupled logic, and a read/write control circuit including a voltage producing section producing a voltage supplied to said third and fourth transistors, said voltage producing section including an impedance converter for supplying said voltage to said thitd and fourth transistors with a low output impedance, said impedance converter including a fifth transistor of an emitter follower type, wherein said voltage producing section further includes a third diode generating a voltage drop substantially equal to that of said first diode and a sixth transistor having an emitter resistor and a collector resistor and supplying said collector resistor with a current determined by the voltage drop of said third diode and said emitter resistor, the potential at the collector of said sixth transistor being supplied to said fifth transistor.

Claim 13

A memory device comprising a plurality of memory cells each including first and second transistors forming a flip-flop circuit, a first parallel circuit of a first resistor and a first diode provided as a load of said first transistor, and a second parallel circuit of a second resistor and a second diode provided as a load of said second transistor, a third transistor cooperating with said first transistor to form an emitter-coupled logic, a fourth transistor cooperating with said second transistor to form an emitter-coupled logic, and a read/write control circuit including a voltage producing section producing a voltage supplied to said third and fourth transistors, said voltage producing section including an impedance converter for supplying said voltage to said thitd and fourth transistors with a low output impedance, said impedance converter including a fifth transistor of an emitter follower type, wherein said voltage producing section further includes a third diode generating a voltage drop substantially equal to that of said first diode and a sixth transistor having an emitter resistor and a collector resistor and supplying said collector resistor with a current determined by the voltage drop of said third diode and said emitter resistor, the potential at the collector of said sixth transistor being supplied to said fifth transistor.