Semiconductor device including Darlington connections

Claim 1

A semiconductor device including a plurality of transistors connected in a Darlington configuration, comprising: a semiconductor substrate, a common collector layer of a first conductivity type deposited on said semiconductor substrate, a plurality of base regions of a second conductivity formed on said common collector layer, corresponding to said plurality of transistors, said plurality of base regions being independent from each other, a plurality of emitter regions of the first conductivity type each formed on each of said plurality of base regions, so that said plurality of transistors are structured, a metallization layer interconnecting base and emitter regions of different ones of said plurality of transistors such that said plurality of transistors are in a Darlington configuration, and a conductor wire connected between a portion of the metallization layer formed on the base region of the transistor of the last stage and a portion of the metallization layer formed on the emitter region of the transistor of the stage preceding the last stage to electrically bypass resistance inherent in the metallization layer.