Superconducting analog-to-digital converter with bidirectional counter

Claim 2

A superconducting analog-to-digital converter, comprising: a double-junction superconducting quantum interference device (SQUID) having first and second Josephson junctions and a center-tapped load inductance; means for applying a constant gate current to the center of the load inductance; means for applying a bidirectionally varying analog signal current to the load inductance, wherein positive incremental changes in the analog signal current result in the generation of voltage pulses across the first junction, and negative incremental changes in the analog current signal result in the generation of voltage pulses of the same polarity aross the second junction; and means for counting the voltage pulses generated across the first and second junctions, to determine the corresponding digital equivalents of the changes in the analog signal current.

Claim 3

A superconducting analog-to-digital converter as set forth in claim 1, wherein the means for counting includes: a plurality of counter stages, each including a SQUID configured as a bistable element and each having a single input terminal for receiving a signal that operates to toggle the state of the stage, a carry output terminal for outputting a carry signal when the stage is toggled from a "1" state to a "0" state, and a borrow output terminal for outputting a borrow signal when the stage is toggled from a "0" state to a "1" state; means for clocking up-count signals and down-count signals into the first stage of the counter; means responsive to an up-count signal, for enabling propagation of a carry signal from one stage to the next in sequence; means responsive to a down-count signal, for enabling propagation of a borrow signal from one stage to the next in sequence; whereby application of up-count and down-count signals to the counter results in ripple addition and ripple subtraction of a binary "1" at the least-significant bit position of the counter.

Claim 4

A superconducting analog-to-digital converter as set forth in claim 2, wherein: the means for enabling propagation of the carry and borrow signals include logic gates implemented in the form of SQUID's.

Claim 5

A superconducting analog-to-digital converter as set forth in claim 2, wherein: the means for enabling propagation of the carry and borrow signals include logic gates implemented in the form of double-junction SQUID's.

Claim 6

A superconducting analog-to-digital converter as set forth in claim 2, wherein the means for counting further includes: means for sensing the count value stored in the counter.

Claim 7

A superconducting analog-to-digital converter, comprising: an inductance having a center-tap terminal and two terminals; first and second Josephson junctions, each having first and second terminals, the first terminals being connected together and the second terminal being connected to opposite end terminals of the inductance; means for applying a constant gate current to the center-tap terminal of the inductance; means for applying a bidirectionally varying analog signal current to the inductance, wherein positive inremental changes in the analog signal current result in the generation of voltage pulses across the first junction, and negative incremental changes in the analog signal current result in the generation of voltage pulses of the same polarity across the second junction; and means for counting the voltage pulses generated across the first and second junctions, to determine the corresponding digital value of the changes in the analog signal current.

Claim 8

A superconducting analog-to-digital converter, comprising: an inductance having a center-tap terminal and two terminals; first and second Josephson junctions, each having first and second terminals, the first terminals being connected together and the second terminal being connected to opposite end terminals of the inductance; means for applying a constant gate current to the center-tap terminal of the inductance; means for applying a bidirectionally varying analog signal current to the inductance, wherein positive inremental changes in the analog signal current result in the generation of voltage pulses across the first junction, and negative incremental changes in the analog signal current result in the generation of voltage pulses of the same polarity across the second junction; and means for counting the voltage pulses generated across the first and second junctions, to determine the corresponding digital value of the changes in the analog signal current.

Claim 9

A superconducting analog-to-digital converter as set forth in claim 6, wherein the means for counting includes: a plurality of counter stages, each including a SQUID configured as a bistable element and each having a single input terminal for receiving a signal that operates to toggle the state of the stage, a carry output terminal for outputting a carry signal when the stage is toggled from a "1" state to a "0" state, and a borrow output terminal for outputting a borrow signal when the stage is toggled from "0" state to a "1" state; means for clocking up-count signals and downcount signals into the first stage of the counter; means responsive to an up-count signal, for enabling propagation of a carry signal from one stage to the next in sequence; means responsive to a down-count signal, for enabling propagation of a borrow signal from one stage to the next in sequence; whereby application of up-count and downcount signals to the counter results in ripple addition and ripple subtraction of a binary "1" at the least-significant bit position of the counter.

Claim 10

A superconducting analog-to digital converter as set forth in claim 7, wherein: the means for enabling propagation of the carry and borrow signals include logic gates implemented in the form of SQUID's.

Claim 11

A superconducting analog-to digital converter as set forth in claim 7, wherein the means for counting further includes: means for sensing the count value stored in the counter.

Claim 12

A superconducting bidirectional counter, comprising: a plurality of counter stages, each including a SQUID configured as a bistable element and each having a single input terminal for receiving a signal that operates to toggle the state of the stage, a carry output terminal for outputting a carry signal when the stage is toggled from a "1" state to a "0" state, and a borrow output terminal for outputting a borrow signal when the stage is toggled from a "0" state to a "1" state; means for clocking up-count signals and down-count signals to the first stage of the counter; means responsive to an up-count signal, for enabling propagation of a carry signal from one stage to the next in sequence; means responsive to a down-count signal, for enabling propagation of a borrow signal from one stage to the next in sequence; whereby application of up-count and down-count signals to the counter results in ripple addition and ripple subtraction of a binary "1" at the least-significant bit position of the counter.

Claim 13

A superconducting bidirectional counter, comprising: a plurality of counter stages, each including a SQUID configured as a bistable element and each having a single input terminal for receiving a signal that operates to toggle the state of the stage, a carry output terminal for outputting a carry signal when the stage is toggled from a "1" state to a "0" state, and a borrow output terminal for outputting a borrow signal when the stage is toggled from a "0" state to a "1" state; means for clocking up-count signals and down-count signals to the first stage of the counter; means responsive to an up-count signal, for enabling propagation of a carry signal from one stage to the next in sequence; means responsive to a down-count signal, for enabling propagation of a borrow signal from one stage to the next in sequence; whereby application of up-count and down-count signals to the counter results in ripple addition and ripple subtraction of a binary "1" at the least-significant bit position of the counter.

Claim 14

A superconducting bidrectional counter as set forth in claim 10, wherein: the means for enabling propagation of the carry and borrow signals include logic gates implemented in the form of SQUID's.

Claim 15

A superconducting bidirectional counter as set forth in claim 10, wherein: the means for enabling propagation of the carry and borrow signals include logic gates implemented in the form of double-junction SQUID's.

Claim 16

A superconducting bidirectional counter as set forth in claim 10, wherein the means for counting further includes: means for sensing the count value stored in the counter.