← Back to Patent Explorer
US4645707A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor devices

Assignee: The General Electric Company PLC
•
Filing: 1985-11-19
•
Granted: 1987-02-24
•
Expires: 2005-11-19
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor device incorporating two superlattices in the GaAs/AlGaAs system separated by a relatively thick layer of GaAlAs is described. The device displays negative differential conductance.

Inventors

  • 👤 Richard A. Davies
  • 👤 Michael J. Kelly

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 06:02
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/81; H10D62/815; H10D62/8161; H10D62/8162; H10D62/8164; H10D8/00; H10D8/70; Y; Y10; Y10S; Y10S428/00; Y10S428/901; Y10T; Y10T428/00; Y10T428/24; Y10T428/24942; Y10T428/2495

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 134 words
A semiconductor device exhibiting negative differential conductance, the device comprising two superlattices each comprising alternating layers of two different semiconductor materials such that there is a misalignment of energy band edges between each pair of adjacent layers with the layers of one of the materials constituting potential barriers to charge carriers passing through each superlattices, said superlattices being coupled to each other by a barrier layer of semiconductor material forming respective heterojunctions with the adjacent layers of the superlattices, said barrier layer having a lower transmission coefficient for said charge carriers than said layers of said one material, said superlattices defining the allowed energy levels of said charge carriers at either side of said barrier layer, and the value of a potential applied across said barrier layer determining the current-voltage characteristics of the device.
Claim 2
Dependent Claim 134 words
A semiconductor device exhibiting negative differential conductance, the device comprising two superlattices each comprising alternating layers of two different semiconductor materials such that there is a misalignment of energy band edges between each pair of adjacent layers with the layers of one of the materials constituting potential barriers to charge carriers passing through each superlattices, said superlattices being coupled to each other by a barrier layer of semiconductor material forming respective heterojunctions with the adjacent layers of the superlattices, said barrier layer having a lower transmission coefficient for said charge carriers than said layers of said one material, said superlattices defining the allowed energy levels of said charge carriers at either side of said barrier layer, and the value of a potential applied across said barrier layer determining the current-voltage characteristics of the device.
Claim 3
Dependent Claim 33 words
A device according to claim 1 in which said one material and the material of said barrier layer is Al x Ga 1-x As, and the other material in each superlattice is GaAs.
Claim 4
Dependent Claim 11 words
A device according to claim 2 in which χ is 0.45.
Claim 5
Dependent Claim 28 words
A device according to claim 2 in which said layers of GaAs are doped with silicon to put the Fermi level in the first miniband for each superlattice.
Claim 6
Dependent Claim 29 words
A device according to claim 4 in which said layers of GaAs are doped in a region spaced away from the adjacent layers of Al x Ga 1-x As.
Claim 7
Dependent Claim 24 words
A device according to claim 1 in which said barrier layer is at least twice as thick as said layers of said one material.
Claim 8
Dependent Claim 18 words
A device according to claim 1 in which each of said superlattices is of at least three periods.
Claim 9
Dependent Claim 30 words
A device according to claim 1 in which the width of the first miniband for each of said superlattices is less than the optic phonon energy for said one material.
Claim 10
Dependent Claim 11 words
A device according to claim 2 in which χ is 0.25.

References Cited (Backward Citations)

US4517047A Cited
US4511408A Cited
US4503447A Cited
US4558336A Cited
US4591889A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-02-23 1990-08-25 1991-02-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-02-23 1994-08-25 1995-02-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-02-23 1998-08-25 1999-02-24 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag