Low error rate digital demodulator

Claim 2

In a digital demodulator for demodulating a carrier input signal on which data is modulated at a predetermined baud rate, the combination of, a signal source of substantially the same frequency as said carrier but asynchronous therewith, means controlled by said signal source for sampling said modulated carrier signal at twice carrier rate, means for continuously storing the last three samples of said sampling means, means operating at carrier rate for producing a first output pulse when the pattern of said last three samples is one-zero-one and producing a second output pulse when the pattern of said last three samples is zero-one-zero, and means for separately counting said first and second output pulses and producing an output signal of predetermined logic value when either the number of first pulses or the number of second pulses counted during a predetermined interval exceeds a predetermined percentage of the number of carrier cycles in said interval.

Claim 3

The combination of claim 1 wherein said predetermined interval is one sixth of a bit interval at said predetermined baud rate.

Claim 4

The combination of claim 1, wherein said predetermined baud rate is 300 and said predetermined interval is one sixth of a bit interval at said baud rate.

Claim 5

The combination of claim 1, wherein said predetermined baud rate is 1200 and said predetermined interval is one sixth of a bit interval at said baud rate.

Claim 6

The combination of claim 1, which includes means for counting the number of said output signals produced during a bit interval and outputting a logic "1" if the number of output signals counted exceeds a predetermined percentage of the number of said predetermined intervals in one bit interval.

Claim 7

The combination of claim 5, wherein said predetermined percentage of output signals counted is two thirds.

Claim 8

The combination of claim 1, wherein said carrier input signal has a frequency of 115.2 kHz.

Claim 9

The combination of claim 1, wherein said predetermined percentage is 75%.

Claim 10

The combination of claim 1 which includes second sampling means controlled by said signal source for sampling said modulated carrier signal at twice carrier rate and at points on the carrier spaced 90° from the sampling points of said first named sampled means, means for continuously storing the last three samples of said second sampling means, means operating at carrier rate for producing a third output pulse when the pattern of said last three samples of said second sampling means is one-zero-one and producing a fourth output pulse when the pattern of said last three samples is zero-one-zero, and means for separately counting said third and fourth output pulses and producing an output signal of predetermined logic value when either the number of third pulses or the number of fourth pulses counted during a predetermined interval exceeds a predetermined percentage of the number of carrier cycles in said interval.

Claim 11

A digital demodulator for demodulating a carrier signal which is keyed on and off in accordance with data bits occurring at a predetermined baud rate, a first source of timing signals occurring at approximately twice the frequency of said carrier signal but asynchronous therewith, first sampling means controlled by said first timing signals for continuously sampling said carrier signal, means for continuously storing the last three samples of said first sampling means, means operating at one half the frequency of said timing signals for producing a pulse on first output terminal each time the pattern of said last three samples is one-zero-one and producing a pulse on a second output terminal each time the pattern of said last three samples is zero-one-zero, a counter connected to said first output terminal and another counter connected to said second output terminal means for resetting said counters at a rate which is a predetermined multiple of said baud rate and means for producing an output pulse each time either of said counter reaches a predetermined count before it is reset.

Claim 12

A digital demodulator for demodulating a carrier signal which is keyed on and off in accordance with data bits occurring at a predetermined baud rate, a first source of timing signals occurring at approximately twice the frequency of said carrier signal but asynchronous therewith, first sampling means controlled by said first timing signals for continuously sampling said carrier signal, means for continuously storing the last three samples of said first sampling means, means operating at one half the frequency of said timing signals for producing a pulse on first output terminal each time the pattern of said last three samples is one-zero-one and producing a pulse on a second output terminal each time the pattern of said last three samples is zero-one-zero, a counter connected to said first output terminal and another counter connected to said second output terminal means for resetting said counters at a rate which is a predetermined multiple of said baud rate and means for producing an output pulse each time either of said counter reaches a predetermined count before it is reset.

Claim 13

A digital demodulator as set forth in claim 10, wherein said predetermined count is equal to three fourths of the number of carrier cycles in the interval between resetting of said counters.

Claim 14

A digital demodulator as set forth in claim 10, which includes a source of second timing signals occurring 180° out of phase with said first timing signals, second sampling means controlled by said second timing signals for continuously sampling said carrier signal, and means for continuously storing the last three samples of said second sampling means.

Claim 15

A digital demodulator as set forth in claim 12, which includes means operating at one half the frequency of said timing signals for producing a pulse on a third output terminal each time the pattern of said last three samples of said second sampling means is one-zero-one and producing a pulse on a fourth output terminal each time the pattern of said last three samples of said second sampling means is zero-one-zero.

Claim 16

A digital demodulator as set forth in claim 13, which includes a counter connected to each of said third and fourth output terminals, means for resetting said counters connected to said third and fourth terminals at the same rate as said first named counters, and means for producing an output pulse each time any one of said counters reaches a predetermined count before it is reset.

Claim 17

A digital demodulator as set forth in claim 14, wherein said predetermined count is equal to three fourths of the number of carrier cycles in the interval between the resetting of said counters.

Claim 18

Means for detecting the presence of a signal component of predetermined frequency in an output signal which includes undesired noise components, comprising a plural stage shift register, means for applying said input signal to the data input of said shift register, means for asynchronously clocking the stages of said register at a frequency twice said predetermined frequency so that the stages of said register are successively set in accordance with the value of said input signal when said stages are clocked, means for combining the outputs of said shift register stages to produce a first output pulse when said inputs and outputs have a one-zero-one sequence pattern or a second output pulse when said inputs and outputs have a zero-one-zero sequence pattern, said combining means comprising first and second exclusive OR gates each having inputs, an input on the first exclusive OR gate being connected to the input of the first stage, the other input of the first exclusive OR gate being connected to the output of the first stage, an input of the second exclusive OR gate being connected to the input of the second stage, the other input of the second exclusive OR gate being connected to the output of the second stage, and means for detecting one of said sequence patterns including means for ending the outputs of said two exclusive OR gates.

Claim 19

Means for detecting the presence of a signal component of predetermined frequency in an output signal which includes undesired noise components, comprising a plural stage shift register, means for applying said input signal to the data input of said shift register, means for asynchronously clocking the stages of said register at a frequency twice said predetermined frequency so that the stages of said register are successively set in accordance with the value of said input signal when said stages are clocked, means for combining the outputs of said shift register stages to produce a first output pulse when said inputs and outputs have a one-zero-one sequence pattern or a second output pulse when said inputs and outputs have a zero-one-zero sequence pattern, said combining means comprising first and second exclusive OR gates each having inputs, an input on the first exclusive OR gate being connected to the input of the first stage, the other input of the first exclusive OR gate being connected to the output of the first stage, an input of the second exclusive OR gate being connected to the input of the second stage, the other input of the second exclusive OR gate being connected to the output of the second stage, and means for detecting one of said sequence patterns including means for ending the outputs of said two exclusive OR gates.

Claim 20

The combination of claim 16, which includes means for developing strobe pulses at said predetermined frequency, and means controlled in part by said strobe pulses for developing said first and second output pulses.