Satellite-receiver time division multiple-access burst duration and guard space monitor

Claim 2

A burst duration and guard space signal generator circuit for use in TDMA telecommunications systems comprising: means for sampling a received detected QPSK envelope signal at a rate greater than a symbol rate of said envelope signal; burst duration signal producing means operating in response to a first predetermined number of successive samples of said detected envelope signal for outputting said burst duration signal in an active state when at least one of said first predetermined number of samples of said detected envelope signals are in a first logic state; guard space signal producing means operating in response to said burst duration signal producing means for outputting said guard space signal in an active state if and only if said burst duration signal has been in an inactive state for a predetermined second number of samples; and wherein said burst duration signal generating means comprises first shift register means having at least two bit outputs and receiving an output from said sampling means and a first OR gate having inputs coupled to each of said bit outputs of said first shift register means, said burst duration signal being generated at an output of said first OR gate.

Claim 3

The burst duration and guard space signal generating circuit of claim 1 wherein said guard space signal generating means comprises second shift register means receiving an inverted output from said first OR gate; and a second OR gate having inputs coupled to each bit output of said second shift register, said guard space signal being generated on an output of said second OR gate.

Claim 4

The burst duration and guard space signal generating circuit of claim 2 wherein said sampling means comprises means for generating a clock signal at twice said symbol rate of said envelope signal and means for adjusting a phase of said clock signal relative to a phase of said envelope signal.

Claim 5

The burst duration and guard space monitor circuit of claim 3 wherein said sampling means comprises a flip-flop receiving said clock signal, said clock signal also being coupled to clock inputs of said first and second shift registers.

Claim 6

The burst duration and guard space signal generating circuit of any of claims 1, 2, 3 or 4 wherein said first number is three and said second number is four.

Claim 7

A burst duration and guard space signal generating circuit comprising: detector means receiving a QPSK modulated signal; a first low-pass filter having an input coupled to an output of said detector means; a comparator having a first comparison input coupled to an output of said first low-pass filter and a second input coupled to a variable source of a threshold voltage; a master slave flip-flop having a data input coupled to an output of said comparator; a three-bit first shift register having a data input coupled to an output of said master-slave flip-flop; a first OR gate having inputs coupled to each bit output of said first shift register, said burst duration signal being produced on an output of said first OR gate; a four-bit second shift register receiving an inverted output from said first OR gate; a second OR gate having inputs coupled to each bit output of said second shift register, said guard space signal being produced on an output of said second OR gate; a second low-pass filter receiving a clock signal having a frequency corresponding to a symbol rate of said QPSK signal; a frequency doubler having an input coupled to an output of said second low-pass filter; an adjustable delay circuit having a signal input coupled to an output of said frequency doubler and a signal output coupled to clock inputs of said flip-flop and said first and second shift registers; and programmable switch means coupled to delay time control inputs of said adjustable delay circuit.

Claim 8

A burst duration and guard space signal generating circuit comprising: detector means receiving a QPSK modulated signal; a first low-pass filter having an input coupled to an output of said detector means; a comparator having a first comparison input coupled to an output of said first low-pass filter and a second input coupled to a variable source of a threshold voltage; a master slave flip-flop having a data input coupled to an output of said comparator; a three-bit first shift register having a data input coupled to an output of said master-slave flip-flop; a first OR gate having inputs coupled to each bit output of said first shift register, said burst duration signal being produced on an output of said first OR gate; a four-bit second shift register receiving an inverted output from said first OR gate; a second OR gate having inputs coupled to each bit output of said second shift register, said guard space signal being produced on an output of said second OR gate; a second low-pass filter receiving a clock signal having a frequency corresponding to a symbol rate of said QPSK signal; a frequency doubler having an input coupled to an output of said second low-pass filter; an adjustable delay circuit having a signal input coupled to an output of said frequency doubler and a signal output coupled to clock inputs of said flip-flop and said first and second shift registers; and programmable switch means coupled to delay time control inputs of said adjustable delay circuit.

Claim 9

The burst duration and guard space generating circuit of any of claims 1, 2, 3 or 4 wherein said sampling means samples said detected envelope signal at a rate twice the symbol rate of said detected envelope signal.