Diagnostic method for addressing arrangement verification

Claim 1

In a processing system including a processor, a plurality of printed wiring cards (PWCs) having a plurality of sense points or control points, an addressing arrangement for selectively enabling said PWCs via a data bus connecting said processor to each said PWC, a diagnostic method for validating the integrity of said addressing arrangement comprising the steps of: first selecting a first address having first and second address components corresponding to a first particular PWC having a plurality of sense points; first testing a second PWC corresponding to a second address having a different first address component and an identical second address component as said first address and producing a first valid or a first invalid condition; second selecting a third PWC corresponding to a third address having an identical first address component and a second address component incremented by one as said first address in response to said invalid first condition; second testing a fourth PWC corresponding to a fourth address having an identical first address component and a second address component incremented by one as said second address in response to said invalid first condition to produce a second valid or a second invalid condition; first indicating a fault for said PWC corresponding to said second address and a fault for said second address component of said first address in response to said second valid condition; second indicating a fault for said first address component of said first address in response to said second invalid condition; first iterating said steps first and second selecting, first and second testing and first and second indicating with an address having said first address component incremented by one for each said step of first iterating for each of said first address components; third selecting a fifth address, having first and second address components, corresponding to a fifth PWC having a plurality of sense points; third testing a sixth PWC corresponding to a sixth address having an identical first address component and second address component incremented by one as said fifth address, said third testing producing a third valid or a third invalid condition; fourth selecting a seventh PWC corresponding to a seventh address having a first address component incremented by one and a second address component identical to said fifth address in response to said third invalid condition; fourth testing an eighth address having an identical first address component and a second address incremented by one as said seventh address, said fourth testing producing a fourth invalid condition or a fourth valid condition in response to said third invalid condition; third indicating a fault for said PWC corresponding to said fifth address and a fault for said first address component of said fifth address in response to said fourth valid condition; fourth indicating a fault for said second address component of said fifth address in response to said fourth invalid condition; and second iterating said steps of first iterating, third and fourth selecting, third and fourth testing and third and fourth indicating with an address having said second address component incremented by one for each said step of second iterating for each of said second address components.