High-speed switching processor for a burst-switching communications system

Claim 1

A high-speed switching processor for use in a switch of a burst-switching communications system, a burst being a plurality of bytes, said system including a plurality of switches interconnected by time-division multiplexed communications links, each link having a plurality of frames within each second of time, each frame having a plurality of channels, each channel having communications capacity for the transmission of one byte, a byte being a predetermined number of bits, a bit being one binary digit, said system including a plurality of ports, each port being a component of a switch, said switch including at least one switching processor, a queue sequencer, a character memory, and a channel clock, said character memory and queue sequencer each having a respective bus coupled therewith, said switching processor comprising: (a) a data/address bus; (b) control means coupled with said data/address bus for controlling said switching processor, said control means including stored-program memory and execution means, said control means having means for receiving and being responsive to a signal from said channel clock; (c) jump-address means coupled with said data/address bus and said control means, for generating a jump address based on character-state and channel-state and for transmitting said jump address to said control means, said jump-address means operating substantially in parallel with and independently of said control means; (d) external-interface means coupled with said data/address bus for providing an interface between said switching processor and said communications links and ports, said external-interface means having the ability to receive a byte in the current channel from a communication link or port, said external-interface means operating substantially in parallel with and independently of said control means; (e) character-memory interface means coupled with said data/address bus for providing an interface between said switching processor and said character memory, said character-memory interface means having the ability to read or write a byte from said character memory, said character-interface means operating substantially in parallel with and independently of said control means; (f) queue-sequencer interface means coupled with said data/address bus for providing an interface between said switching processor and said queue sequencer, said queue-sequencer interface means having the ability to receive a buffer address from the queue sequencer, said queue-sequencer interface means operating substantially in parallel with and independently of said control means and said queue sequencer; and (g) buffer-address means coupled between said queue-sequencer interface means and said character-memory interface means for generating a buffer address based on the channel number, said buffer-address means having the ability to receive said buffer address from said queue-sequencer interface means, said buffer address means operating substantially in parallel with and independently of said control means; (h) said jump-address means being coupled with said external-interface means and having the ability to receive a byte of a burst from said external-interface means; (i) said control means having the ability to receive said jump address from said jump-address means and to transfer processing control to the instruction in said stored-program memory located at the address indicated by said jump address.