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US4644388A
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Process and circuit for the demodulation of chrominance signals
Assignee: Thales SA
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Filing: 1984-12-06
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Granted: 1987-02-17
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Expires: 2004-12-06
Abstract
Abstract The present invention relates to chrominance decoding circuits and more particularly to a novel circuit for demodulating chrominance signals, B-Y or R-Y. This circuit comprises, connected in series, a multiplier multiplying the U or V-modulated chrominance signal by itself, a filter giving at the output the square (B-Y) 2 or (R-Y) 2 of the chrominance signal, a device for extracting the square root giving an absolute value .tbd.B-Y.tbd. or .tbd.R-Y.tbd. of the chrominance signal, and a multiplier multiplying said absolute value by the sign of the chrominance signal B-Y or R-Y to obtain at the output said chrominance signal, B-Y or R-Y.
Inventors
- 👤 Patrick Douziech
- 👤 Michel Imbert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:35
CPC Classifications
H; H04; H04N; H04N11/00; H04N11/06; H04N11/12; H04N11/14; H04N11/16; H04N11/165
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
98 words
A process for the demodulation of each of chrominance signals B-Y and R-Y, comprising, for each of said chrominance signals, the steps of: demodulating a modulated chrominance signal by itself and providing a first output; filtering said first output so as to retain the square of said chrominance signal; extracting the square root of said retained square of said chrominance value in order to obtain the absolute value of said chrominance signal; and multiplying said absolute value by the sign of the chrominance signal obtained by said step of demodulating in order to obtain a final chrominance signal.
Claim 2
Dependent Claim
98 words
A process for the demodulation of each of chrominance signals B-Y and R-Y, comprising, for each of said chrominance signals, the steps of: demodulating a modulated chrominance signal by itself and providing a first output; filtering said first output so as to retain the square of said chrominance signal; extracting the square root of said retained square of said chrominance value in order to obtain the absolute value of said chrominance signal; and multiplying said absolute value by the sign of the chrominance signal obtained by said step of demodulating in order to obtain a final chrominance signal.
Claim 3
Dependent Claim
117 words
A circuit for demodulating each of two modulated chrominance signals, comprising, for each modulated chrominance signal; a multiplying means for multiplying a modulated chrominance signal by itself in order to obtain a squared value output; a filter means being fed with said squared value output and outputting a square of a final unmodulated chrominance signal; means for extracting the square root of said square of said final chrominance signal in order to provide an absolute value of said final chrominance signal; a second multiplying means for multiplying said absolute value by the sign of the signal output from said first multiplier in order to obtain a final unmodulated chrominance signal have both a sign and a magnitude.
Claim 4
Dependent Claim
117 words
A circuit for demodulating each of two modulated chrominance signals, comprising, for each modulated chrominance signal; a multiplying means for multiplying a modulated chrominance signal by itself in order to obtain a squared value output; a filter means being fed with said squared value output and outputting a square of a final unmodulated chrominance signal; means for extracting the square root of said square of said final chrominance signal in order to provide an absolute value of said final chrominance signal; a second multiplying means for multiplying said absolute value by the sign of the signal output from said first multiplier in order to obtain a final unmodulated chrominance signal have both a sign and a magnitude.
Claim 5
Dependent Claim
41 words
A circuit according to claim 2 further comprising a comparator which compares the chrominance signal from said first multiplier means with a reference signal corresponding to zero wherein the output of said comparator provides said sign of said final chrominance signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-16 | 1990-08-18 | 1991-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-16 | 1994-08-18 | 1995-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-16 | 1998-08-18 | 1999-02-17 | $7700.00 | Window Closed / Lapsed |