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US4644185A Expired / Lapsed US ⏱️ 0.0 years remaining

Self clocking CMOS latch

Assignee: National Semiconductor Corp
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Filing: 1985-05-03
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Granted: 1987-02-17
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Expires: 2005-05-03
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Abstract

Abstract A CMOS latch is coupled to a differential driver that is operated from the input data. Driver conduction is determined by the conduction in a strobe transistor responding to the signal of a strobe line. The strobe line is normally operated at a level that turns the strobe transistor off. The strobe line is coupled to the output of a four input comparator which senses the DATA IN, DATA IN, DATA OUT and DATA OUT. So long as the DATA IN and DATA OUT are in agreement the strobe line will remain at the level that holds the strobe transistor off and the latch will remain in its original state. However, if there is a disagreement the comparator will produce an output that turns the strobe transistor on and the device will then reset the latch. Thus, the circuit will only change its latch state when the input logic changes.

Inventors

  • 👤 Ronald C. Todd

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 04:52
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/35613; H03K3/356017; H03K3/356034

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 112 words
A self clocking latch circuit comprising: a latch having DATA and DATA output terminals; differentially conducting driver means coupled to said DATA and DATA output terminals for forcing said latch to one of two states; differentially conducting sense means coupled to respond to the state of said latch and to a DATA input signal to form a comparator that compares said latch state and said DATA input and produces an output strobe signal when said latch state and said DATA input are in disagreement; and means responsive to said output strobe signal for rendering said differentially conducting driver means operative to force said latch to the state represented by said DATA input.
Claim 2
Dependent Claim 112 words
A self clocking latch circuit comprising: a latch having DATA and DATA output terminals; differentially conducting driver means coupled to said DATA and DATA output terminals for forcing said latch to one of two states; differentially conducting sense means coupled to respond to the state of said latch and to a DATA input signal to form a comparator that compares said latch state and said DATA input and produces an output strobe signal when said latch state and said DATA input are in disagreement; and means responsive to said output strobe signal for rendering said differentially conducting driver means operative to force said latch to the state represented by said DATA input.
Claim 3
Dependent Claim 24 words
The circuit of claim 1 wherein said latch is formed by cross coupling a pair of inverters across said DATA and DATA output terminals.
Claim 4
Dependent Claim 53 words
The circuit of claim 1 wherein said differentially conducting driver means comprise a pair of transistors having outputs coupled to said DATA and DATA output terminals of said latch and transistor means coupled in common with said pair of transistors and responsive to said output strobe signal for conduction of said transistor means.
Claim 5
Dependent Claim 36 words
The circuit of claim 1 wherein said differentially conducting sense means comprise a four input comparator coupled to said DATA and DATA output terminals of said latch and to said DATA input and the complement thereof.
Claim 6
Dependent Claim 24 words
The circuit of claim 3 further including latch change enable means coupled to said transistor means coupled in common with said pair of transistors.
Claim 7
Dependent Claim 31 words
The circuit of claim 4 further including compare inhibit means coupled between a voltage supply and said four input comparator to control the flow of current in said four input comparator.

References Cited (Backward Citations)

US4247791A Cited
US4506171A Cited
US4567389A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-02-16 1990-08-18 1991-02-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-02-16 1994-08-18 1995-02-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-02-16 1998-08-18 1999-02-17 $7700.00 Window Closed / Lapsed

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