Patent US4642544A successfully refreshed from Google Patents.
US4642544A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Control circuit for driving step motor
Assignee: Mitsubishi Electric Corp
•
Filing: 1985-08-07
•
Granted: 1987-02-10
•
Expires: 2005-08-07
Abstract
Abstract A control circuit for driving a step motor with at least first and second phase coils each having corresponding phase control elements. A memory stores phase switching data and is connected to the phase control elements. A first counter supplies phase switching data addresses to the memory to identify the coil or coils and phase thereof to be driven in response to step driving pulses and a second counter supplies data addresses to control the ON/OFF of the phase switching data and hence the phase current value. An oscillator drives the second counter at a frequency greater than the frequency of the step driving pulses.
Inventors
- 👤 Takashi Furumura
- 👤 Takeo Ohba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:26
CPC Classifications
H; H02; H02P; H02P8/00; H02P8/14; H02P8/18
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
195 words
A control circuit for driving. in response to step driving pulses, a step motor with at least first and second phase coils each having corresponding phase control elements, said control circuit comprising: memory means for storing phase switching data to control said phase control elements and having a plurality of output terminals adapted to be connected to said phase control elements for supplying phase switching signals to said phase control elements and first and second sets of input terminals for receiving data addresses; a first address counter having output terminals connected to said first set of terminals for successively supplying phase switching data addresses to said memory means in response to said step driving pulses and an input terminal adapted for receiving said step driving pulses; a second address counter having output terminals connected to said second set of terminals for successively supplying data addresses to said memory means to determine the on/off status of said phase switching data and an input terminal for receiving clock pulses; and pulse generating means connected to said input of said second counter for supplying clock pulses at a frequency greater than the frequency of said step driving pulses.
Claim 2
Dependent Claim
195 words
A control circuit for driving. in response to step driving pulses, a step motor with at least first and second phase coils each having corresponding phase control elements, said control circuit comprising: memory means for storing phase switching data to control said phase control elements and having a plurality of output terminals adapted to be connected to said phase control elements for supplying phase switching signals to said phase control elements and first and second sets of input terminals for receiving data addresses; a first address counter having output terminals connected to said first set of terminals for successively supplying phase switching data addresses to said memory means in response to said step driving pulses and an input terminal adapted for receiving said step driving pulses; a second address counter having output terminals connected to said second set of terminals for successively supplying data addresses to said memory means to determine the on/off status of said phase switching data and an input terminal for receiving clock pulses; and pulse generating means connected to said input of said second counter for supplying clock pulses at a frequency greater than the frequency of said step driving pulses.
Claim 3
Dependent Claim
199 words
In combination: a step motor with at least first and second phase coils each having corresponding phase control elements; and a control circuit for driving said step motor in response to step driving pulses, including (1) memory means for storing phase switching data to control said phase control elements and having a plurality of output terminals connected to said phase control elements for supplying phase switching signals to said phase control elements and first and second sets of input terminals for receiving said data addresses, (2) a first address counter having output terminals connected to said first set of terminals for successively supplying phase switching data addresses to said memory means in response to said step driving pulses and an input terminal for receiving said step driving pulses, (3) a second address counter having output terminals connected to said second set of terminals for successively supplying data addresses to said memory means to determine the on/off status of said phase switching data and an input terminal for receiving clock pulses, and (4) pulse generating means connected to said input of said second counter for supplying clock pulses at a frequency greater than the frequency of said step driving pulses.
Claim 4
Dependent Claim
199 words
In combination: a step motor with at least first and second phase coils each having corresponding phase control elements; and a control circuit for driving said step motor in response to step driving pulses, including (1) memory means for storing phase switching data to control said phase control elements and having a plurality of output terminals connected to said phase control elements for supplying phase switching signals to said phase control elements and first and second sets of input terminals for receiving said data addresses, (2) a first address counter having output terminals connected to said first set of terminals for successively supplying phase switching data addresses to said memory means in response to said step driving pulses and an input terminal for receiving said step driving pulses, (3) a second address counter having output terminals connected to said second set of terminals for successively supplying data addresses to said memory means to determine the on/off status of said phase switching data and an input terminal for receiving clock pulses, and (4) pulse generating means connected to said input of said second counter for supplying clock pulses at a frequency greater than the frequency of said step driving pulses.
References Cited (Backward Citations)
US4476421A
Cited
US4528491A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-09 | 1990-08-11 | 1991-02-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-09 | 1994-08-11 | 1995-02-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-09 | 1998-08-11 | 1999-02-10 | $7700.00 | Window Closed / Lapsed |