Method and circuit arrangement for the transmission of data signal bits occurring with a first bit rate in a bit stream having a second bit rate which is higher than the first bit rate

Claim 3

The method of claim 1, and further comprising the steps of: forming the first bit group by a standard bit (X); and forming the second bit group by two identical bits (X,Y).

Claim 4

The method of claim 1, and further comprising the steps of: forming the first bit group by two different bits (X,Y); and forming the second bit group by two identical bits (X,Y).

Claim 5

A circuit arrangement for transmitting data signal bits occurring in a first bit rate from a transmission device via a transmission link to a receiving device in a bit stream having a second bit rate which is higher in comparison to the first bit rate, said circuit arrangement comprising: a transmitting device, a receiving device and a transmission link interconnecting said transmitting device and said receiving device, said transmitting device operable to receive data bits at a first bit rate and transmit the data bits over said transmission link at a second bit rate which is higher than the first bit rate and said receiving device operable to receive the data bits from said transmission link at said second bit rate and output the same at said first bit rate; said transmitting device connected to said transmission link and comprising a transmission data buffer for intermediately storing the data signal bits received at the first bit rate and operable to emit the data signal bits at the second bit rate, said transmitting device comprising a bit group emission means connected to said transmission data buffer for emitting a fixed bit group (X; X, Y) from at least two different bit groups for transmission via said transmission link either before or after reading of a fixed plurality of bits from said transmission data buffer, whereby the one bit group together with its bits transmitted from the transmission data buffer is identified as belonging to a data signal envelope, whereas the other bit group together with its bits transmitted from the transmission data buffer is identified as belonging to a blank envelope; a first control arrangement in said transmission device connected to said transmission data buffer and operable, after respective identification of the fixed plurality of data signal bits to be accommodated in an envelope to produce a control signal for reading of the appertaining bits from said transmission data buffer and controlling the emission of the one bit group or the other bit group before or after reading; a receiving data buffer in said receiving device connected to said transmission link for intermediately storing the data bits received from said transmission link at the second bit rate; and a second control arrangement in said receiving device connected to said receiving data buffer for controlling the storage of the data signal bits received at the second bit rate such that only the data signal bits belonging to the data signal envelope are stored in and then read from said receiving data buffer.

Claim 6

A circuit arrangement for transmitting data signal bits occurring in a first bit rate from a transmission device via a transmission link to a receiving device in a bit stream having a second bit rate which is higher in comparison to the first bit rate, said circuit arrangement comprising: a transmitting device, a receiving device and a transmission link interconnecting said transmitting device and said receiving device, said transmitting device operable to receive data bits at a first bit rate and transmit the data bits over said transmission link at a second bit rate which is higher than the first bit rate and said receiving device operable to receive the data bits from said transmission link at said second bit rate and output the same at said first bit rate; said transmitting device connected to said transmission link and comprising a transmission data buffer for intermediately storing the data signal bits received at the first bit rate and operable to emit the data signal bits at the second bit rate, said transmitting device comprising a bit group emission means connected to said transmission data buffer for emitting a fixed bit group (X; X, Y) from at least two different bit groups for transmission via said transmission link either before or after reading of a fixed plurality of bits from said transmission data buffer, whereby the one bit group together with its bits transmitted from the transmission data buffer is identified as belonging to a data signal envelope, whereas the other bit group together with its bits transmitted from the transmission data buffer is identified as belonging to a blank envelope; a first control arrangement in said transmission device connected to said transmission data buffer and operable, after respective identification of the fixed plurality of data signal bits to be accommodated in an envelope to produce a control signal for reading of the appertaining bits from said transmission data buffer and controlling the emission of the one bit group or the other bit group before or after reading; a receiving data buffer in said receiving device connected to said transmission link for intermediately storing the data bits received from said transmission link at the second bit rate; and a second control arrangement in said receiving device connected to said receiving data buffer for controlling the storage of the data signal bits received at the second bit rate such that only the data signal bits belonging to the data signal envelope are stored in and then read from said receiving data buffer.

Claim 7

The circuit arrangement of claim 4, wherein: said first control arrangement of said transmission device comprises a counter for counting a predetermined number of data signal bits to be accommodated in an envelope and operable to control the reading of the data signal bits previously deposited in said transmission data buffer and the transmission of a first or second bit group by said bit group emission device.

Claim 8

The circuit arrangement of claim 5, wherein: said first control arrangement of said transmission device comprises a phase matching device for controlling the times at which the bits stored in said transmission data buffer are read.

Claim 9

The circuit arrangement of claim 6, wherein: said first control arrangement of said transmission device comprises a signal emission device connected to and controlled by said counter for defining the time ranges within which a data signal envelope or a blank envelope is output.

Claim 10

The circuit arrangement of claim 7, wherein: said second control arrangement of said receiving device comprises a bit group evaluation device and a signal emission device for controlling the writing and reading of the respective data signal bits into and out of said receiving data buffer, respectively.

Claim 11

The circuit arrangement of claim 8, wherein: said signal emission device of said receiving device includes means for outputting its write or, respectively, read signals, a logic element for receiving the write and read signals and clock pulses at the second or, respectively, first bit rate.

Claim 12

The circuit arrangement of claim 9, wherein: said second control arrangement of said receiving device comprises a counter for defining the times at which data signal bits are capable of appearing in individual envelopes.

Claim 13

The circuit arrangement of claim 10, wherein: each of said first and second control arrangements respectively comprises a speed decoder operable in response to the feed of a signal at a first bit rate to allow the respective signal emission device for reading data signal bits from the transmission data buffer or, respectively, writing data signals into said receiving data buffer to be effectively controlled.