US4471480A — Programmable controller for a TDM digital multipl…

Claim 1

Independent Claim 430 words

In a digital time division multiplex multiplexer-demultiplexer combination at one communication terminal to multiplex N input data signals each having a predetermined bit rate into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the sam of said predetermined bit rates and to demultiplex N output data signals each having said predetermined bit rate from a received synchronous data stream having said data format and said given bit rate, where N is an integer greater than one, a common controller coupled to a common timing signal generator and each of N channel printed circuit board plug-in receptacles each coupled to a different one of said N input data signals and a different one of N outputs each for a different one of said N output signals, each of said N receptacles having plugged therein a selected one of no printed circuit board, a digital data channel printed circuit board and a frequency shift keying (FSK) channel printed circuit board to process a mixture of digital data signals, teletype signals and FSK signals in said N input data signals and said received data stream, said mixture of signals being in any random order and mix and said digital channel printed circuit boards and said FSK channel printed circuit boards being plugged in said N receptacles in any random order and mix, said controller at least controlling said N receptacles for multiplexing said N input data signals to provide said transmitted data stream and for demultiplexing said received data stream to distribute said N output data signals to appropriate ones of said N outputs, said transmitted data stream and said received data stream having an even distribution of said N input data signals and said N output data signals, respectively, even if certain ones of said N receptacles have no printed circuit board plugged therein, said controller further controlling said timing signal generator for aligning receive timing signals with said data format of said received data signals to provide receive frame synchronization to enable proper demultiplexing of said received data stream, said controller comprising: a programmed digital sequencer executing a series of instructions to control said multiplexing, said demultiplexing and said frame synchronization, said sequencer including program memory means to supply a plurality of digital codes each related to a different one of said series of instructions, and support logic means coupled to said memory means, said N receptacles and said timing generator responsive to said plurality of digital codes to provide control signals for said multiplexing, said demultiplexing and said frame synchronization.

Claim 2

Dependent Claim 430 words

In a digital time division multiplex multiplexer-demultiplexer combination at one communication terminal to multiplex N input data signals each having a predetermined bit rate into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the sam of said predetermined bit rates and to demultiplex N output data signals each having said predetermined bit rate from a received synchronous data stream having said data format and said given bit rate, where N is an integer greater than one, a common controller coupled to a common timing signal generator and each of N channel printed circuit board plug-in receptacles each coupled to a different one of said N input data signals and a different one of N outputs each for a different one of said N output signals, each of said N receptacles having plugged therein a selected one of no printed circuit board, a digital data channel printed circuit board and a frequency shift keying (FSK) channel printed circuit board to process a mixture of digital data signals, teletype signals and FSK signals in said N input data signals and said received data stream, said mixture of signals being in any random order and mix and said digital channel printed circuit boards and said FSK channel printed circuit boards being plugged in said N receptacles in any random order and mix, said controller at least controlling said N receptacles for multiplexing said N input data signals to provide said transmitted data stream and for demultiplexing said received data stream to distribute said N output data signals to appropriate ones of said N outputs, said transmitted data stream and said received data stream having an even distribution of said N input data signals and said N output data signals, respectively, even if certain ones of said N receptacles have no printed circuit board plugged therein, said controller further controlling said timing signal generator for aligning receive timing signals with said data format of said received data signals to provide receive frame synchronization to enable proper demultiplexing of said received data stream, said controller comprising: a programmed digital sequencer executing a series of instructions to control said multiplexing, said demultiplexing and said frame synchronization, said sequencer including program memory means to supply a plurality of digital codes each related to a different one of said series of instructions, and support logic means coupled to said memory means, said N receptacles and said timing generator responsive to said plurality of digital codes to provide control signals for said multiplexing, said demultiplexing and said frame synchronization.

Claim 3

Dependent Claim 100 words

A controller according to claim 1, wherein said memory means includes a program memory having an address input, a data code output and an operation code output, a counter coupled to said data code output, said operation code output, said address input and said timing generator to provide addresses for said memory, a first register coupled to said timing generator and said data code output to store said data code, and a second register coupled to said timing generator and said operation code output to store said operation code, said first and second registers providing said plurality of digital codes.

Claim 4

Dependent Claim 34 words

A controller according to claim 2, wherein said memory means further includes a parity checking means coupled to said data code output and said operation code output for parity checking in said memory means.

Claim 5

Dependent Claim 260 words

A controller according to claims 1, 2 or 3, wherein said data format includes a plurality of channel data time slots, and a plurality of overhead time slots distributed in a given manner throughout said format; and said support logic means includes logic circuitry coupled to said timing genertor, a data rate code bus, a receive bus for said received data stream, a transmit bus for said transmitted data stream, each of said N receptacles and said first and second registers to monitor a transmit clock signal produced by said timing generator equal to said given rate, to logically determine which of a selected one of said input data signals and an overhead bit is to be gated into said transmitted data stream for any given time slot of said data format and produce first control signals to be coupled to an appropriate one of said N receptacles when an input data signal is to be gated into said transmitted data stream in a first predetermined period of time and in a second predetermined period of time different than and spaced from said first period of time respond to overhead bits of said overhead time slots of said received data stream to provide said frame synchronization and then for each period of a received clock signal produced by said timing generator equal to said given rate produce second control signals to extract said output data signals from said received data stream, said first and second control signals being dependent upon said data rate present on said data rate code bus.

Claim 6

Dependent Claim 79 words

A controller according to claim 4, further including built-in test equipment coupled to said timing generator and each of said N receptacles responsive to a fault in said controller, said timing generator and any of said printed circuit boards to provide a fault signal to light a fault indicator at that one of said controller, said timing generator and said printed circuit boards producing said fault and to activate a front panel summary fault indicator and an audible alarm.

Claim 7

Dependent Claim 41 words

A controller according to claim 5, wherein said test equipment further includes means coupled to said received data stream to detect whether said given bit rate is within predetermined limits and if not to light a front panel traffic fault indicator.

Claim 8

Dependent Claim 55 words

A controller according to claim 6, wherein at least one of each of said first and second control signals is coupled to an associated one of said N receptacles to provide on said data rate code bus a code indicating an absence of a printed circuit board in said associated one of said N receptacles.

Claim 9

Dependent Claim 100 words

A controller according to claims 1, 2 or 3, further including built-in test equipment coupled to said timing generator and each of said N receptacles responsive to a fault in said controller, said timing generator and any of said printed circuit boards to provide a fault signal, each of said controller, said timing generator and said printed circuit boards having a fault indicator, said fault signal lighting said fault indicator at that one of said controller, said timing generator and said printed circuit boards producing said fault and to activate a front panel summary fault indicator and an audible alarm.

Claim 10

Dependent Claim 41 words

A controller according to claim 8, wherein said test equipment further includes means coupled to said received data stream to detect whether said given bit rate is within predetermined limits and if not to light a front panel traffic fault indicator.

Claim 11

Dependent Claim 51 words

A controller according to claim 9, wherein at least one of said control signals is coupled to each of said N receptacles in sequence to provide on a data rate control bus a code indication that a printed circuit board is not plugged in an associated one of said N receptacles.

Claim 12

Dependent Claim 42 words

A controller according to claims 1, 2 or 3, further including built-in test equipment coupled to said received data stream to detect whether said given bit rate is within predetermined limits and if not to light a front panel traffic fault indicator.

Claim 13

Dependent Claim 51 words

A controller according to claim 11, wherein at least one of said control signals is coupled to each of said N receptacles in sequence to provide on a data rate control bus a code indication that a printed circuit board is not plugged in an associated one of said N receptacles.

Claim 14

Dependent Claim 54 words

A controller according to claims 1, 2 or 3, wherein at least one of said control signals is coupled to each of said N receptacles in sequence to provide on a data rate control bus a code indication that a printed circuit board is not plugged in an associated one of said N receptacles.

Claim 15

Dependent Claim 197 words

A controller according to claims 1, 2 or 3, wherein said predetermined bit rate of each of said N input data signals are different, said N input data signals having a first random mixture of said different bit rates and said N output data signals having a second random mixture of said different bit rates, and said sequencer further includes first means coupled to each of said N receptacles to sequentially determine said bit rate of each of said N input data signals, and second means coupled to said first means and said memory means to determine whether the sum of said bit rates for said N input data signals exceeds said given bit rate, said second means inhibiting time slot assignment in said data format for said N input data signals and activating a front panel indicator if said given bit rate is exceeded and producing codes for each time slot of said data format to cause assignment of data bits of each of said N input data signals with equal spacing throughout said time slots of said data format if said given bit rate is not exceeded, said codes being coupled to said memory means.

Claim 16

Dependent Claim 55 words

A controller according to claim 14, wherein said second means causes time slot assignment of data bits of said N input data signals in a decreasing order from that one of said N input data signals having the highest bit rate to that one of said N input data signals having the lowest bit rate.

Claim 17

Dependent Claim 257 words

A controller according to claim 15, wherein said data format includes a plurality of channel data time slots, and a plurality of overhead time slots distributed in a given manner throughout said format; and said support logic means includes logic circuitry coupled to said timing generator, a data rate code bus, a receive bus for said received data stream, a transmit bus for said transmitted data stream, each of said N receptacles and said first and second registers to monitor a transmit clock signal produced by said timing generator equal to said given rate, to logically determine which of a selected one of said input data signals and an overhead bit is to be gated into said transmitted data stream for any given time slot of said data format and produce first control signals to be coupled to an appropriate one of said N receptacles when an input data signal is to be gated into said transmitted data stream in a first predetermined period of time and in a second predetermined period of time different than and spaced from said first period of time respond to overhead bits of said overhead time slots of said received data stream to provide said frame synchronization and then for each period of a received clock signal produced by said timing generator equal to said given rate produce second control signals to extract said output data signals from said received data stream, said first and second control signals being dependent upon said data rate present on said data rate code bus.

Claim 18

Dependent Claim 79 words

A controller according to claim 16, further including built-in test equipment coupled to said timing generator and each of said N receptacles responsive to a fault in said controller, said timing generator and any of said printed circuit boards to provide a fault signal to light a fault indicator at that one of said controller, said timing generator and said printed circuit boards producing said fault and to activate a front panel summary fault indicator and an audible alarm.

Claim 19

Dependent Claim 41 words

A controller according to claim 17, wherein said test equipment further includes means coupled to said received data stream to detect whether said given bit rate is within predetermined limits and if not to light a front panel traffic fault indicator.

Claim 20

Dependent Claim 55 words

A controller according to claim 18, wherein at least one of each of said first and second control signals is coupled to an associated one of said N receptacles to provide on said data rate code bus a code indicating an absence of a printed circuit board in said associated one of said N receptacles.

Claim 21

Dependent Claim 256 words

A controller according to claim 14, wherein said data format includes a plurality of channel data time slots, and a plurality of overhead time slots distributed in a given manner throughout said format; and said support logic means includes logic circuitry coupled to said timing generator, a data rate code bus, a receive bus for said received data stream, a transmit bus for said transmitted data stream, each of said N receptacles and said first and second registers to monitor a transmit clock signal produced by said timing generator equal to said given rate, to logically determine which of a selected one of said input data signals and an overhead bit is to be gated into said transmitted data stream for any given time slot of said data format and produce first control signals to be coupled to an appropriate one of said N receptacles when an input data signal is to be gated into said transmitted data stream in a first predetermined period of time and in a second period of time different than and spaced from said first period of time respond to overhead bits of said overhead time slots of said received data stream to provide said frame synchronization and then for each period of a received clock signal produced by said timing generator equal to said given rate produce second control signals to extract said output data signals from said received data stream, said first and second control signals being dependent upon said data rate present on said data rate code bus.

Claim 22

Dependent Claim 79 words

A controller according to claim 20, further including built-in test equipment coupled to said timing generator and each of said N receptacles responsive to a fault in said controller, said timing generator and any of said printed circuit boards to provide a fault signal to light a fault indicator at that one of said controller, said timing generator and said printed cicuit boards producing said fault and to activate a front panel summary fault indicator and an audible alarm.

Claim 23

Dependent Claim 41 words

A controller according to claim 21, wherein said test equipment further includes means coupled to said received data stream to detect whether said given bit rate is within predetermined limits and if not to light a front panel traffic fault indicator.

Claim 24

Dependent Claim 55 words

A controller according to claim 22, wherein at least one of each of said first and second control signals is coupled to an associated one of said N receptacles to provide on said data rate code bus a code indicating an absence of a printed circuit board in said associated one of said N receptacles.

Claim 25

Dependent Claim 79 words

A controller according to claim 14, further including built-in test equipment coupled to said timing generator and each of said N receptacles responsive to a fault in said controller, said timing generator and any of said printed circuit boards to provide a fault signal to light a fault indicator at that one of said controller, said timing generator and said printed circuit boards producing said fault and to activate a front panel summary fault indicator and an audible alarm.

Claim 26

Dependent Claim 41 words

A controller according to claim 24, wherein said test equipment further includes means coupled to said received data stream to detect whether said given bit rate is within predetermined limits and if not to light a front panel traffic fault indicator.

Claim 27

Dependent Claim 51 words

A controller according to claim 25, wherein at least one of said control signals is coupled to each of said N receptacles in sequence to provide on a data rate control bus a code indication that a printed circuit board is not plugged in an associated one of said N receptacles.

Claim 28

Dependent Claim 39 words

A controller according to claim 14, further including built-in test equipment coupled to said received data stream to detect whether said given bit rate is within predetermined limits and if not to light a front panel traffic fault indicator.

Claim 29

Dependent Claim 51 words

A controller according to claim 27, wherein at least one of said control signals is coupled to each of said N receptacles in sequence to provide on a data rate control bus a code indication that a printed circuit board is not plugged in an associated one of said N receptacles.

Claim 30

Dependent Claim 51 words

A controller according to claim 14, wherein at least one of said control signals is coupled to each of said N receptacles in sequence to provide on a data rate control bus a code indication that a printed circuit board is not plugged in an associated one of said N receptacles.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1987-09-11	1988-03-12	1988-09-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1991-09-11	1992-03-12	1992-09-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1995-09-11	1996-03-12	1996-09-11	$7700.00	Window Closed / Lapsed

Programmable controller for a TDM digital multiplexer-demultiplexer combination

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