Vector processor having pair process mode and single process mode

Claim 2

A vector processor for carrying out vector instructions which designate a plurality of vectors by performing operations on vector elements belonging to the vectors comprising: a main storage; a plurality of vector registers; means, including a plurality of vector data transfer circuits, for performing data transfer between said main storage and said vector registers; means, including a plurality of vector arithmetic units coupled to said vector registers and each capable of performing the same arithmetic operations, for carrying out vector instructions by performing arithmetic operations on vector data received from said vector registers and sending the results to a vector register; detecting means for detecting whether a vector instruction to be carried out is a first type of vector instruction designating operations between vector elements having the same element number or a second type of vector instruction designating operations between vector elements having different element numbers; and control means responsive to said detecting means for controlling the execution of a vector arithmetic operation in a first or second control mode in response to the type of the vector instruction detected by said detecting means, wherein said first control mode includes dividing vector registers and vector arithmetic units into a plurality of sets and dividing vector data to be operated on by a vector arithmetic instruction into a plurality of vector data portions, thereby to process the plurality of vector data portions in parallel using said plurality of sets, and said second control mode includes storing each vector data in corresponding vector registers, thereby to perform the vector arithmetic operation using the vector arithmetic units which operate together with said vector registers.

Claim 3

A vector processor according to claim 1, wherein among the vector processing, simple vector instructions consisting of only the operations which are to be executed between vector elements which have the same element number are executed in said first control mode, and wherein the complicated vector instructions which require operations between vector elements which have different element numbers are executed in said second control mode.

Claim 4

A vector processor for carrying out vector instructions which designate a plurality of vectors by performing operations on vector elements belonging to the vectors comprising: a main storage; a plurality of vector registers; means, including a plurality of vector data transfer circuits, for performing data transfer between said main storage and said vector registers; means, including a plurality of vector arithmetic units coupled to said vector registers and each capable of performing the same arithmetic operations, for carrying out the vector arithmetic instructions by performing arithmetic operations on the vector data received from said vector registers and for sending the results to the vector register; detecting means for detecting whether a vector instruction to be carried out is a first type of vector instruction designating operations between vector elements having the same element number of a second type of vector instruction designating operations between vector elements at least one of which is obtained as the result of another operation previously executed; and control means responsive to said detecting means for controlling the execution of a vector arithmetic operation in a first or second control mode in response to the type of the vector instruction detected by said detecting means, wherein said first control mode includes dividing vector registers and vector arithmetic units into a plurality of sets and dividing vector data to be operated by a vector arithmetic instruction into a plurality of vector data portions, thereby to process the plurality of vector data portions in parallel using said plurality of sets, and wherein said second control mode includes storing each vector data in corresponding vector registers, thereby to perform the vector arithmetic operation using the vector arithmetic units which operate together with said vector registers.

Claim 5

A vector processor for carrying out vector instructions which designate a plurality of vectors by performing operations on vector elements belonging to the vectors comprising: a main storage; a plurality of vector registers; means, including a plurality of vector data transfer circuits, for performing data transfer between said main storage and said vector registers; means, including a plurality of vector arithmetic units coupled to said vector registers and each capable of performing the same arithmetic operations, for carrying out the vector arithmetic instructions by performing arithmetic operations on the vector data received from said vector registers and for sending the results to the vector register; detecting means for detecting whether a vector instruction to be carried out is a first type of vector instruction designating operations between vector elements having the same element number of a second type of vector instruction designating operations between vector elements at least one of which is obtained as the result of another operation previously executed; and control means responsive to said detecting means for controlling the execution of a vector arithmetic operation in a first or second control mode in response to the type of the vector instruction detected by said detecting means, wherein said first control mode includes dividing vector registers and vector arithmetic units into a plurality of sets and dividing vector data to be operated by a vector arithmetic instruction into a plurality of vector data portions, thereby to process the plurality of vector data portions in parallel using said plurality of sets, and wherein said second control mode includes storing each vector data in corresponding vector registers, thereby to perform the vector arithmetic operation using the vector arithmetic units which operate together with said vector registers.

Claim 6

A vector processor for carrying out vector instructions which designate a plurality of vectors by performing operations on vector elements belonging to the vectors comprising: a main storage; a plurality of vector registers; means, including a plurality of vector data transfer circuits, for performing data transfer between said main storage and said vector registers; means, including a plurality of vector arithmetic units coupled to said vector registers and each capable of performing the same arithmetic operations, for carrying out vector arithmetic instructions by performing arithmetic operations on the vector data received from said vector registers and for sending the results of the arithmetic operations to the vector registers; control means, having a plurality of general purpose register and connected to receive from said main storage a vector start instruction instructs start of processing of a series of vector instructions, for storing data indicative of the type of vector instruction in one of said general-purpose registers designated by the vector start instruction, said type of the vector instruction being a first type of vector instruction designating operations between vector elements having the same element number or a second type of vector instruction designating operations between vector elements having different element numbers, and for controlling said vector processor to execute a vector arithmetic operation in a first or second control mode in accordance with indication of the data stored in said one of the general purpose registers, wherein said first control mode includes dividing vector registers and vector arithmetic units into a plurality of sets and dividing vector data to be operated by a vector arithmetic instruction into a plurality of vector data portions, thereby to process the plurality of vector data portions in parallel using said plurality of sets, and wherein said second control mode includes storing each vector data in corresponding vector registers, thereby to perform the vector arithmetic operation using vector arithmetic units which operate together with said vector registers.

Claim 7

A vector processor for carrying out vector instructions which designate a plurality of vectors by performing operations on vector elements belonging to the vectors comprising: a main storage; a plurality of vector registers; means, including a plurality of vector data transfer circuits, for performing data transfer between said main storage and said vector registers; means, including a plurality of vector arithmetic units coupled to said vector registers and each capable of performing the same arithmetic operations, for carrying out vector arithmetic instructions by performing arithmetic operations on the vector data received from said vector registers and for sending the results of the arithmetic operations to the vector registers; control means, having a plurality of general purpose register and connected to receive from said main storage a vector start instruction instructs start of processing of a series of vector instructions, for storing data indicative of the type of vector instruction in one of said general-purpose registers designated by the vector start instruction, said type of the vector instruction being a first type of vector instruction designating operations between vector elements having the same element number or a second type of vector instruction designating operations between vector elements having different element numbers, and for controlling said vector processor to execute a vector arithmetic operation in a first or second control mode in accordance with indication of the data stored in said one of the general purpose registers, wherein said first control mode includes dividing vector registers and vector arithmetic units into a plurality of sets and dividing vector data to be operated by a vector arithmetic instruction into a plurality of vector data portions, thereby to process the plurality of vector data portions in parallel using said plurality of sets, and wherein said second control mode includes storing each vector data in corresponding vector registers, thereby to perform the vector arithmetic operation using vector arithmetic units which operate together with said vector registers.