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US4641247A
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Bit-sliced, dual-bus design of integrated circuits
Assignee: Advanced Micro Devices Inc
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Filing: 1985-08-30
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Granted: 1987-02-03
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Expires: 2005-08-30
Abstract
Abstract A monolithic integrated circuit chip preferably includes a pair of data busses capable of conducting in parallel the number of signals which can be processed simultaneously by the components on the chip. Signals on the busses are carried in a time-multiplexed manner, each bus having a predetermined number of time slots. Preferably, each component on the chip is connected to one or both of the busses and is assigned a particular time slot for the bus to which it is connected. The resulting chip is of a structured, rather than a custom, design. Accordingly, it can be readily expanded or contracted in the number of signals which can be simultaneously processed. The number of components which can be included on the chip is limited only by the number of time slots available on the bus to which it is connected. By providing two busses, such common circuit elements as two-input adder/subtractors can be readily accommodated by a chip designed according to the instant invention. The bit-slice organization of the chip significantly reduces the design effort of the components connected to a bus, since a one-bit slice is merely replicated for each conductor of the bus. Ease of expansion along this dimension is achieved at virtually no cost.
Inventors
- 👤 Ronald C. Laugesen
- 👤 Padmanabha I. Venkitakrishnan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:02
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; G06F15/7896
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
105 words
A portion of a monolithic integrated circuit chip performing operations in parallel on a plurality of signals, comprising: at least two plural-conductor time-division multiplexed bidirectional busses, each having a conductor carrying one of said plurality of signals operated on by said chip portion; and a plurality of circuit elements each performing parallel operations on a predetermined one of said plurality of signals; wherein each said circuit element is assigned a predetermined time-division slot of at least one of said busses and each said circuit element comprises a plurality of subelements each connected to a predetermined one of said conductors of said at least one bus.
Claim 2
Dependent Claim
105 words
A portion of a monolithic integrated circuit chip performing operations in parallel on a plurality of signals, comprising: at least two plural-conductor time-division multiplexed bidirectional busses, each having a conductor carrying one of said plurality of signals operated on by said chip portion; and a plurality of circuit elements each performing parallel operations on a predetermined one of said plurality of signals; wherein each said circuit element is assigned a predetermined time-division slot of at least one of said busses and each said circuit element comprises a plurality of subelements each connected to a predetermined one of said conductors of said at least one bus.
Claim 3
Dependent Claim
22 words
A monolithic integrated circuit chip portion according to claim 1 wherein predetermined ones of said subelements of a circuit element are replicated.
Claim 4
Dependent Claim
68 words
A monolithic integrated circuit chip portion according to claim 1 responsive to a plural-phase clock signal wherein predetermined ones of said circuit elements are sources for a predetermined one of said busses during said predetermined time-division slots assigned to said circuit elements, and predetermined ones of said circuit elements are destinations for a predetermined one of said busses during said predetermined time-division slots assigned to said circuit elements.
Claim 5
Independent Claim
122 words
A method of designing a portion of a monolithic integrated circuit chip performing operations in parallel on a plurality of signals, comprising the steps of: (a) providing at least two plural-conductor time-division multiplexed bidirectional busses, each having a conductor carrying one of said plurality of signals operated on by said chip portion; (b) including a plurality of circuit elements each performing parallel operations on a predetermined one of said plurality of signals; (c) assigning each said circuit element a time-division slot on at least one of said busses; (d) forming each said circuit element of a plurality of subelements; and (e) connecting each said subelement of said circuit element to a predetermined one of said conductors of said at least one bus.
Claim 6
Independent Claim
122 words
A method of designing a portion of a monolithic integrated circuit chip performing operations in parallel on a plurality of signals, comprising the steps of: (a) providing at least two plural-conductor time-division multiplexed bidirectional busses, each having a conductor carrying one of said plurality of signals operated on by said chip portion; (b) including a plurality of circuit elements each performing parallel operations on a predetermined one of said plurality of signals; (c) assigning each said circuit element a time-division slot on at least one of said busses; (d) forming each said circuit element of a plurality of subelements; and (e) connecting each said subelement of said circuit element to a predetermined one of said conductors of said at least one bus.
Claim 7
Dependent Claim
30 words
A monolithic integrated circuit chip portion design method according to claim 4 wherein step (d) further calls for forming predetermined ones of said subelements of a circuit element by replication.
Claim 8
Dependent Claim
83 words
A monolithic integrated circuit chip portion design method according to claim 4 wherein said chip portion is responsive to a plural-phase clock signal, further including the steps of: (f) assigning predetermined ones of said circuit elements as sources for a predetermined one of said busses during said predetermined time-division slots assigned to said circuit elements; and (g) assigning predetermined ones of said circuit elements as destinations for a predetermined one of said busses during said predetermined time-division slots assigned to said circuit elements.
Claim 9
Dependent Claim
96 words
A monolithic integrated circuit chip portion design method according to claim 4, further providing a method of adding circuit elements included in said chip portion, comprising the further steps of: (h) extending the length of said busses provided at step (a); (i) assigning each said added circuit element a time-division slot on at least one of said extended busses; (j) forming each said added circuit element of a plurality of subelements; and (k) connecting each said subelement of said added circuit element to a predetermined one of said conductors of said at least one extended bus.
Claim 10
Dependent Claim
106 words
A monolithic integrated circuit chip portion design method according to claim 4, further providing a method of increasing the number of said plurality of signals which can be operated on in parallel by said chip, comprising the further steps of: (l) adding a predetermined number of conductors to said busses provided at step (a); (m) adding subelements forming each said circuit element in the amount of said conductors added at step (1); and (n) connecting each said subelement added to said circuit element at step (m) to a predetermined one of said conductors added to said busses at step (1) of said at least one bus.
References Cited (Backward Citations)
US4583179A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-02 | 1990-08-04 | 1991-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-02 | 1994-08-04 | 1995-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-02 | 1998-08-04 | 1999-02-03 | $7700.00 | Window Closed / Lapsed |