Patent US4639893A successfully refreshed from Google Patents.
US4639893A
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Self-aligned split gate EPROM
Assignee: WAFER SCALE INTEGRATION Inc 4633 OLD IRONSIDE DRIVE SUITE 420 SANTA CLARA CA 95050 A CA CORP
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Filing: 1984-05-15
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Granted: 1987-01-27
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Expires: 2004-05-15
Abstract
Abstract A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. The control gate formed over the floating gate controls the portion of the channel region between the floating gate and the source to provide split gate operation. The source region is formed sufficiently far from the floating gate so that the channel length between the source region and the closest edge of the floating gate is controlled by the control gate but does not have to be accurately defined.
Inventors
- 👤 Boaz Eitan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:22
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
122 words
A self-aligned split gate single transistor memory cell for a programmable read only memory comprising a semiconductor substrate containing a source region and a drain region separated by a channel region; a floating gate formed over but insulated from a first portion of the channel region, a first edge of the floating gate being aligned with and used to define one edge of said drain region and a second edge of said floating gate being over said channel region and separated from the closest edge of said source region by a second portion of said channel region; and a control gate formed over but insulated from said floating gate and formed over but insulated from said second portion of said channel region.
Claim 2
Dependent Claim
122 words
A self-aligned split gate single transistor memory cell for a programmable read only memory comprising a semiconductor substrate containing a source region and a drain region separated by a channel region; a floating gate formed over but insulated from a first portion of the channel region, a first edge of the floating gate being aligned with and used to define one edge of said drain region and a second edge of said floating gate being over said channel region and separated from the closest edge of said source region by a second portion of said channel region; and a control gate formed over but insulated from said floating gate and formed over but insulated from said second portion of said channel region.
Claim 3
Dependent Claim
52 words
Structure as in claim 1 wherein that portion of said control gate overlying said second portion of said channel region is separated from the second portion of said channel region by insulation of approximately the same thickness as the insulation separating said floating gate from said first portion of said channel region.
Claim 4
Dependent Claim
65 words
Structure as in claim 1 wherein the minimum length of said second portion of said channel region from said source region to said floating gate is a function of the alignment tolerances on the manufacturing process used to make said memory cell and wherein the length of said second portion of said channel can vary by substantial amounts without affecting the performance of said cell.
Claim 5
Dependent Claim
33 words
Structure as in claim 3 wherein the length of said second portion of said channel region can vary by in excess of 1 micron without substantially affecting the performance of the memory cell.
Claim 6
Dependent Claim
47 words
Structure as in claim 1 wherein said floating gate has a portion which extends over a portion of said drain due to the lateral diffusion of said drain region under said floating gate during the processing of said memory cell after the formation of said drain region.
Claim 7
Dependent Claim
32 words
Structure as in claim 1 wherein said single transistor memory cell is part of an array of such cells each cell having approximately the same effective channel length underneath its floating gate.
Claim 8
Dependent Claim
38 words
Structure as in claim 1 wherein said floating gate is formed prior to the drain region and the drain region is then formed using one edge of the floating gate to define one edge of the drain region.
References Cited (Backward Citations)
US4274012A
Cited
US4412311A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-26 | 1990-07-28 | 1991-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-26 | 1994-07-28 | 1995-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-26 | 1998-07-28 | 1999-01-27 | $7700.00 | Window Closed / Lapsed |