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US4639891A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signals path control circuitry for a data terminal
Assignee: Digital Equipment Corp
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Filing: 1983-11-14
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Granted: 1987-01-27
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Expires: 2003-11-14
Abstract
Abstract The present invention is related to clearing a communication path and in the alternative blocking said communication path between a data terminal and a main data processor, when it appears, from said terminal end, that the data path into the main computer is blocked by some system irregularity in a first case, or should be blocked because of a data overflow condition, in a second case. The present system employs a pair of buffers, the first of which is connected in said communication path, while the second buffer is connected in a data path along which data signals are transmitted from the main data processor. Said communication path includes first logic circuitry connected between said first buffer device and a UART which is connected to the main data processor. Said first logic circuitry can block or unblock the transmission of data to the main data processor. Second logic circuitry is connected between the second buffer and said UART. Said second logic circuitry includes monitoring circuitry which monitors signals coming from the main data processor so that if an "off" signal is transmitted, then a proper signal will be generated and sent to said first logic circuitry to block data transmission from said terminal.
Inventors
- 👤 Thomas C. Porcher
- 👤 Morgan E. Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:31
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/24; G06F3/00; G06F3/14; G06F3/153; G06F3/01; G06F3/02; G06F3/0227
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
417 words
In a data terminal system which has a data output means including a data display means an output means memory and a keyboard means and which data terminal system is formed to receive from and send data signals to a main data processor, which main data processor transmits coded "on" and "off" signals to said data terminal system to control whether or not said data terminal system transmits signals to said main data processor, an arrangement to alternatively clear and block transmission of signals between said data terminal system and said main data processor comprising in combination: bidirectional signal conversion means formed to convert parallel signals to serial signals and alternatively to convert serial signals to parallel signals, said bidirectional signal conversion means coupled to receive from and send signals to said main data processor; first signal buffer means formed to have first clearing means which can cause said first signal buffer means to be cleared in response to a clear signal and connected to said output means memory to transmit signals thereto for display on said data display means; first logic circuitry including monitoring signal means connected to said bidirectional signal conversion means and to said first buffer means to receive signals to be passed to said first buffer means and monitor said last mentioned signals to detect said coded "on" and "off" signals should either be present; keyboard circuitry means including a clear communication signal means connected to said keyboard; second signal buffer means formed to have second clearing means which can cause said second signal buffer means to be cleared in response to a clear signal and connected to said keyboard circuitry means to receive signals from said keyboard and store the same for further transmission; second logic circuitry connected to said first logic circuitry, to said second buffer means and to said bidirectional signal conversion means to selectively pass data signals to said main data processor through said bidirectional signal conversion means; third circuitry means connected from said clear communication signal means to said first and second buffer means and to said first logic circuitry whereby, in response to a clear communication signal from said keyboard circuitry means, said third circuitry means transmits a clear signal to said first and second clearing means to clear said first and second buffer means and transmits a reset signal to said first logic circuitry to reset said monitor signal means to an "on" condition in the event said monitor signal means is in an "off" condition.
Claim 2
Dependent Claim
417 words
In a data terminal system which has a data output means including a data display means an output means memory and a keyboard means and which data terminal system is formed to receive from and send data signals to a main data processor, which main data processor transmits coded "on" and "off" signals to said data terminal system to control whether or not said data terminal system transmits signals to said main data processor, an arrangement to alternatively clear and block transmission of signals between said data terminal system and said main data processor comprising in combination: bidirectional signal conversion means formed to convert parallel signals to serial signals and alternatively to convert serial signals to parallel signals, said bidirectional signal conversion means coupled to receive from and send signals to said main data processor; first signal buffer means formed to have first clearing means which can cause said first signal buffer means to be cleared in response to a clear signal and connected to said output means memory to transmit signals thereto for display on said data display means; first logic circuitry including monitoring signal means connected to said bidirectional signal conversion means and to said first buffer means to receive signals to be passed to said first buffer means and monitor said last mentioned signals to detect said coded "on" and "off" signals should either be present; keyboard circuitry means including a clear communication signal means connected to said keyboard; second signal buffer means formed to have second clearing means which can cause said second signal buffer means to be cleared in response to a clear signal and connected to said keyboard circuitry means to receive signals from said keyboard and store the same for further transmission; second logic circuitry connected to said first logic circuitry, to said second buffer means and to said bidirectional signal conversion means to selectively pass data signals to said main data processor through said bidirectional signal conversion means; third circuitry means connected from said clear communication signal means to said first and second buffer means and to said first logic circuitry whereby, in response to a clear communication signal from said keyboard circuitry means, said third circuitry means transmits a clear signal to said first and second clearing means to clear said first and second buffer means and transmits a reset signal to said first logic circuitry to reset said monitor signal means to an "on" condition in the event said monitor signal means is in an "off" condition.
Claim 3
Dependent Claim
40 words
In a data terminal system, an arrangement to alternatively clear and block the communication path according to claim 1 wherein said first logic circuitry includes comparator means to detect the presence of said "on" signal and alternatively, said "off" signal.
Claim 4
Dependent Claim
33 words
In a data terminal system, an arrangement to alternatively clear and block the communication path according to claim 2 wherein said monitoring signal means includes a bistable circuit connected to said comparator means.
Claim 5
Dependent Claim
71 words
In a data terminal system, an arrangement to alternatively clear and block the communication path according to claim 1 wherein said second logic circuitry includes an AND gate with an output means connected to said second buffer and one input means adapted to receive clock signals and another input connected to said first logic to receive a blocking signal therefrom in response to said monitoring signal means detecting an "off" signal.
Claim 6
Dependent Claim
66 words
In a data terminal system, an arrangement to alternatively clear and block the communication path according to claim 1 wherein said keyboard circuitry includes first and second signal paths and a multiplexor means connected thereto and wherein said second signal buffer is connected through said multiplexor to said first signal path and said third circuitry means is connected through said multiplexor to said second signal path.
Claim 7
Dependent Claim
29 words
In a data terminal system, an arrangement to alternatively clear and block the communications path according to claim 1 wherein said third circuitry means includes a signal decoder means.
Claim 8
Dependent Claim
60 words
In a data terminal system, an arrangement to alternatively clear and block the communication path according to claim 1 wherein said second logic circuitry includes a signal encoder means and wherein in response to a signal from said third circuitry means said encoder means sends a request to said main computer requesting said main computer to generate an "on" signal.
Claim 9
Dependent Claim
73 words
In a data terminal system, an arrangement to alternatively clear and block the communication path according to claim 1 wherein said first signal buffer means includes means to generate an overload signal if the data stored in said first signal buffer exceeds an upper threshold value and wherein said second logic circuitry is connected to said first signal buffer to respond to said overload signal and request an "off" signal from said computer.
Claim 10
Dependent Claim
85 words
In a data terminal system, an arrangement to alternatively clear and block the communication path according to claim 1 wherein said first signal buffer means includes means to generate an underload signal if the data stored in said first signal buffer is below a lower threshold value and wherein said first signal buffer means is connected to said second logic circuitry to transmit said underload signal thereto whereby said second logic circuitry is formed to respond and request an "on" signal from said main computer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-26 | 1990-07-28 | 1991-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-26 | 1994-07-28 | 1995-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-26 | 1998-07-28 | 1999-01-27 | $7700.00 | Window Closed / Lapsed |