Patent US3986058A successfully refreshed from Google Patents.
Patent US4639856A successfully refreshed from Google Patents.
US4639856A
Expired / Lapsed
US
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Dual stream processor apparatus
Assignee: International Business Machines Corp
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Filing: 1983-11-04
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Granted: 1987-01-27
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Expires: 2003-11-04
Abstract
Abstract A dual stream processor apparatus, for use in a multiprocessor computer system, is disclosed. The multiprocessor computer system includes at least a first processor and a second processor. A first apparatus and a second apparatus is included in both the first processor and the second processor for use when either the first or the second processor is inoperative. The first apparatus, disposed within the inoperative processor, suspends the functional operation of the inoperative processor. The second apparatus, disposed within the inoperative processor, transmits a miss signal to the other remaining functionally operational processor. When the other remaining processor receives the miss signal, it will not subsequently attempt to locate desired data in the cache of the inoperative processor. Rather, the other remaining processor will search for the desired data in the main memory in the event it cannot locate the data in its own cache.
Inventors
- 👤 John Hrustich
- 👤 Wayne R. Sitler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:16
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0793; G06F11/0706; G06F11/0721; G06F11/0724
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
270 words
In a multiprocessor computer system including a plurality of processors, service processor means connected to the plurality of processors for developing an output signal in the event a failure occurs within one of the processors, a main memory connected to the plurality of processors for supplyihg instructions and data, I-module means disposed within each of the processors for preventing a current instruction from being re-executed and a next instruction from being executed in response to a trap signal, and control means disposed within each of the processors for controlling the operation of the processor, remaining ones of said plurality of processors attempting to search for data in the one processor prior to searching for the data in the main memory, said control means of the one processor comprising: first means connected to said service processor means for transmitting a special signal from the one processor to the remaining ones of said plurality of processors in the event said failure occurs within the one processor in response to said output signal from said service processor means, said remaining ones of said plurality of processors neglecting to search for the data in the one processor and searching for the data in the main memory in response to said special signal from said first means of said one processor, said first means including, latch circuit means for generating a set signal in response to said output signal from said service processor means, and gate means for generating an output signal in response to said set signal, said first means transmitting said special signal in response to said output signal from said gate means.
Claim 2
Dependent Claim
270 words
In a multiprocessor computer system including a plurality of processors, service processor means connected to the plurality of processors for developing an output signal in the event a failure occurs within one of the processors, a main memory connected to the plurality of processors for supplyihg instructions and data, I-module means disposed within each of the processors for preventing a current instruction from being re-executed and a next instruction from being executed in response to a trap signal, and control means disposed within each of the processors for controlling the operation of the processor, remaining ones of said plurality of processors attempting to search for data in the one processor prior to searching for the data in the main memory, said control means of the one processor comprising: first means connected to said service processor means for transmitting a special signal from the one processor to the remaining ones of said plurality of processors in the event said failure occurs within the one processor in response to said output signal from said service processor means, said remaining ones of said plurality of processors neglecting to search for the data in the one processor and searching for the data in the main memory in response to said special signal from said first means of said one processor, said first means including, latch circuit means for generating a set signal in response to said output signal from said service processor means, and gate means for generating an output signal in response to said set signal, said first means transmitting said special signal in response to said output signal from said gate means.
Claim 3
Dependent Claim
77 words
The control means of claim 1, further comprising: second means connected to said service processor means for generating said trap signal in the event said failure occurs within the one processor in response to said output signal from said service processor means, said trap signal energizing said I-module means, said I-module means of the one processor preventing a current instruction from being re-executed and preventing a next instruction from being executed in response to said trap signal.
Claim 4
Dependent Claim
299 words
In a multiprocessor computer system including a plurality of processors, service processor means connected to the plurality of processors for developing an output signal in the event a failure occurs within one of the processors, a main memory connected to the plurality of processors for supplying instructions and data, and control means disposed within each of the processors for controlling the operation of the processor, remaining ones of said plurality of processors attempting to search for data in the one processor prior to searching for the data in the main memory, the one processor developing a miss signal in response thereto when said data is not stored in the one processor or said data is stored in the one processor but is not valid, said control means of the one processor comprising: means connected to said service processor means and responding to said miss signal or to said output signal from said service processor means for transmitting a special signal from the one processor to the remaining ones of said plurality of processors in the event said data is not stored in the one processor, said data is stored in the one processor but is not valid, or said failure occurs within the one processor, said remaining ones of said plurality of processors neglecting to search for the data in the one processor and searching for the data in the main memory in response to said special signal, the means for transmitting including, latch circuit means for generating a set signal in response to said output signal from said service processor means, and gate means for generating an output signal in response to said set signal or in response to said miss signal, said means transmitting said special signal in response to said output signal from said gate means.
Claim 5
Dependent Claim
299 words
In a multiprocessor computer system including a plurality of processors, service processor means connected to the plurality of processors for developing an output signal in the event a failure occurs within one of the processors, a main memory connected to the plurality of processors for supplying instructions and data, and control means disposed within each of the processors for controlling the operation of the processor, remaining ones of said plurality of processors attempting to search for data in the one processor prior to searching for the data in the main memory, the one processor developing a miss signal in response thereto when said data is not stored in the one processor or said data is stored in the one processor but is not valid, said control means of the one processor comprising: means connected to said service processor means and responding to said miss signal or to said output signal from said service processor means for transmitting a special signal from the one processor to the remaining ones of said plurality of processors in the event said data is not stored in the one processor, said data is stored in the one processor but is not valid, or said failure occurs within the one processor, said remaining ones of said plurality of processors neglecting to search for the data in the one processor and searching for the data in the main memory in response to said special signal, the means for transmitting including, latch circuit means for generating a set signal in response to said output signal from said service processor means, and gate means for generating an output signal in response to said set signal or in response to said miss signal, said means transmitting said special signal in response to said output signal from said gate means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-26 | 1990-07-28 | 1991-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-26 | 1994-07-28 | 1995-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-26 | 1998-07-28 | 1999-01-27 | $7700.00 | Window Closed / Lapsed |