US4639760A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High power RF transistor assembly
Assignee: NXP USA Inc
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Filing: 1986-01-21
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Granted: 1987-01-27
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Expires: 2006-01-21
Abstract
Abstract An improved high frequency high power transistor assembly capable of delivering 600 watts or more at 100 MHz and higher without the need for water cooling is described. Four transistor die individually mounted on separate BeO ceramic isolators are installed in a recessed cavity in a copper base. The BeO isolators have metallized top surfaces which connect to the backside output contacts of the transistor die and extend toward the centerline of the cavity. They connect to a longitudally arranged input-output assembly centrally located over the center line of the cavity. The input-output assembly has a wrap-around electrode structure which brings the transistor output connections to the upper surface of the assembly for easy bonding to the output leads. The input to the individual die is via individual ballast resistors mounted on the input-output assembly, one per transistor, to provide transistor-to-transistor matching for more uniform current distribution.
Inventors
- 👤 Helge O. Granberg
- 👤 Samuel L. Coffman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:53
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/20; H10W90/00; H10W44/226; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/682; H10W70/685; H10W72/00; H10W72/50; H10W72/531; H10W72/5366; H10W72/541; H10W72/5445; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
379 words
A high power, high frequency transistor unit, comprising: an electrically and thermally conductive base plate having a centerline; at least two separate electrically insulating but thermally conducting isolators disposed in either side of said centerline, each having a first principal face bonded to said base plate and a second principal face opposite said first principal face, wherein said second principal face has thereon a first metal layer; at least two transistor die, each having a signal input contact, a reference contact, and a power output contact, wherein said signal input contact and said reference contact are on a first face of said transistor die and said power output contact is on an opposed second face of said transistor die, and wherein said at least two transistor die are disposed on said isolators, one per isolator, with said power output contact bonded to said first metal layer of said isolator; a ballasted electrical input-output assembly comprising a substantially flat electrically insulating plate having first and second opposed principal faces, wherein said insulating plate extends over and parallel to said centerline and portions of said at least two isolators and bridges between at least two of said at least two isolators located on either side of said centerline; wherein said insulating plate has on said first face a first metal region region forming an input lead for said assembly and at least two ballast resistor regions, one per transistor, each ballast resistor region being located between said input lead and a second metal region coupled to said input contact of one of said transistors; wherein said insulating plate has on said second face an output conductor electrically coupled to said output contacts of said transistors die by said first metal layers on said isolators, and wherein said output conductor extends around an edge of said insulating plate onto said first surface; and first wire bonds extending from said input lead to an external input lead of said assembly, second wire bonds extending from said output lead to an external output lead of said assembly, third wire bonds extending from said reference contacts of said transistor die to said substrate, and fourth wire bonds extending from said second metal regions on said insulating plate to said input contacts of said transistor die.
Claim 2
Dependent Claim
379 words
A high power, high frequency transistor unit, comprising: an electrically and thermally conductive base plate having a centerline; at least two separate electrically insulating but thermally conducting isolators disposed in either side of said centerline, each having a first principal face bonded to said base plate and a second principal face opposite said first principal face, wherein said second principal face has thereon a first metal layer; at least two transistor die, each having a signal input contact, a reference contact, and a power output contact, wherein said signal input contact and said reference contact are on a first face of said transistor die and said power output contact is on an opposed second face of said transistor die, and wherein said at least two transistor die are disposed on said isolators, one per isolator, with said power output contact bonded to said first metal layer of said isolator; a ballasted electrical input-output assembly comprising a substantially flat electrically insulating plate having first and second opposed principal faces, wherein said insulating plate extends over and parallel to said centerline and portions of said at least two isolators and bridges between at least two of said at least two isolators located on either side of said centerline; wherein said insulating plate has on said first face a first metal region region forming an input lead for said assembly and at least two ballast resistor regions, one per transistor, each ballast resistor region being located between said input lead and a second metal region coupled to said input contact of one of said transistors; wherein said insulating plate has on said second face an output conductor electrically coupled to said output contacts of said transistors die by said first metal layers on said isolators, and wherein said output conductor extends around an edge of said insulating plate onto said first surface; and first wire bonds extending from said input lead to an external input lead of said assembly, second wire bonds extending from said output lead to an external output lead of said assembly, third wire bonds extending from said reference contacts of said transistor die to said substrate, and fourth wire bonds extending from said second metal regions on said insulating plate to said input contacts of said transistor die.
Claim 3
Dependent Claim
187 words
A high power, high frequency transistor device, comprising: a metal base having a substantially flat bottomed recess therein; at least two insulating substrate isolators having metallized regions on their upper faces and mounted in said recess by their lower faces; at least two transistor die, smaller than said substrate isolators, each bonded to a first portion of said metallized region of one of said substrate isolators so as to leave exposed a second portion of said metallized region, wherein said second portions of said metallized regions of said at least two substrate isolators are laterally adjacent; and connection means comprising an insulating base with substantially parallel upper and lower faces, with a first conductor region having a portion on said lower face bonded to said second portions of said metallized regions of said substrate isolators and a portion on said upper face and an interconnecting portion therebetween, with a second conductor region on said upper face separated from said first conductor region, and with ballast resistor regions, one per transistor die on said first face connected to said second conductor region and coupled to said transistor die.
Claim 4
Dependent Claim
187 words
A high power, high frequency transistor device, comprising: a metal base having a substantially flat bottomed recess therein; at least two insulating substrate isolators having metallized regions on their upper faces and mounted in said recess by their lower faces; at least two transistor die, smaller than said substrate isolators, each bonded to a first portion of said metallized region of one of said substrate isolators so as to leave exposed a second portion of said metallized region, wherein said second portions of said metallized regions of said at least two substrate isolators are laterally adjacent; and connection means comprising an insulating base with substantially parallel upper and lower faces, with a first conductor region having a portion on said lower face bonded to said second portions of said metallized regions of said substrate isolators and a portion on said upper face and an interconnecting portion therebetween, with a second conductor region on said upper face separated from said first conductor region, and with ballast resistor regions, one per transistor die on said first face connected to said second conductor region and coupled to said transistor die.
Claim 5
Dependent Claim
201 words
A high power semiconductor device assembly comprising: a metal base having a substantially flat bottomed recess therein; at least two insulating substrate isolators having metallized regions on their upper faces and mounted in said recess by their lower faces; at least two semiconductor die, smaller than said substrate isolators, wherein an upper face of each die contains an input contact and a lower face of each die contains an output contact, and wherein said output contact is directly bonded to a first portion of said metallized region of one of said substrate isolators so as to leave exposed a second portion of said metallized region, and wherein said second portions of said metallized regions of said at least two substrate isolators are laterally adjacent; and connection means comprising an insulating base with substantially parallel upper and lower faces, with a first conductor region having a portion on said lower face bonded to said second portions of said metallized regions of said substrate isolators and a portion on said upper face and an interconnecting portion therebetween, and with a second conductor region on said upper face separated from said first conductor region and electrically coupled to said input contact of said die.
Claim 6
Dependent Claim
201 words
A high power semiconductor device assembly comprising: a metal base having a substantially flat bottomed recess therein; at least two insulating substrate isolators having metallized regions on their upper faces and mounted in said recess by their lower faces; at least two semiconductor die, smaller than said substrate isolators, wherein an upper face of each die contains an input contact and a lower face of each die contains an output contact, and wherein said output contact is directly bonded to a first portion of said metallized region of one of said substrate isolators so as to leave exposed a second portion of said metallized region, and wherein said second portions of said metallized regions of said at least two substrate isolators are laterally adjacent; and connection means comprising an insulating base with substantially parallel upper and lower faces, with a first conductor region having a portion on said lower face bonded to said second portions of said metallized regions of said substrate isolators and a portion on said upper face and an interconnecting portion therebetween, and with a second conductor region on said upper face separated from said first conductor region and electrically coupled to said input contact of said die.
Claim 7
Dependent Claim
175 words
A high power semiconductor device assembly comprising: a metal base having a substantially flat bottomed recess therein; at least two insulating substrate isolators having metallized regions on their upper faces and mounted in said recess by their lower faces; at least two semiconductor die, smaller than said substrate isolators, wherein an upper face of each die contains an input contact and a lower face of each die contains an output contact, and wherein said output contact is directly bonded to a first portion of said metallized region of one of said substrate isolators so as to leave exposed a second portion of said metallized region, and wherein said second portions of said metallized regions of said at least two substrate isolators are laterally adjacent; and connection means comprising an insulating base with substantially parallel upper and lower faces, with a first conductor region having a portion on said lower face bonded to said second portions of said metallized regions of said substrate isolators and a portion on said upper face and an interconnecting portion therebetween.
Claim 8
Dependent Claim
175 words
A high power semiconductor device assembly comprising: a metal base having a substantially flat bottomed recess therein; at least two insulating substrate isolators having metallized regions on their upper faces and mounted in said recess by their lower faces; at least two semiconductor die, smaller than said substrate isolators, wherein an upper face of each die contains an input contact and a lower face of each die contains an output contact, and wherein said output contact is directly bonded to a first portion of said metallized region of one of said substrate isolators so as to leave exposed a second portion of said metallized region, and wherein said second portions of said metallized regions of said at least two substrate isolators are laterally adjacent; and connection means comprising an insulating base with substantially parallel upper and lower faces, with a first conductor region having a portion on said lower face bonded to said second portions of said metallized regions of said substrate isolators and a portion on said upper face and an interconnecting portion therebetween.
References Cited (Backward Citations)
US4038677A
Cited
DE2806099A1
Cited
US4408219A
Cited
US4518982A
Cited
JPS5889852A
Cited
JPS5935456A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-26 | 1990-07-28 | 1991-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-26 | 1994-07-28 | 1995-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-26 | 1998-07-28 | 1999-01-27 | $7700.00 | Window Closed / Lapsed |