US4408219A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for connecting in parallel power transistors in very high frequency
Assignee: Thales SA
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Filing: 1980-11-18
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Granted: 1983-10-04
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Expires: 2000-11-18
Abstract
Abstract A device for connecting in parallel high power transistors in very high frequency having a first plate serving as an electrical and thermal earth plane and a second electrically insulating plate supporting two metallized zones for connection respectively to the system of first parallel-connected electrodes of a transistor and a system of second parallel-connected electrodes of the same transistors, the third electrodes being connected to earth. The transistors, in the form of monolithic systems, are respectively placed on electrically insulating and thermally conductive plates welded to the first zone, while connecting the first electrodes to a first series of terminals and connecting the second electrodes to a second series of terminals. The metallized zones are respectively connected to the terminals of each series by conductors passing through the second electrically insulating plate, the transistors being inserted between the first and second plates.
Inventors
- 👤 Jean C. Resneau
- 👤 Marius Cirio
- 👤 Jean Doyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:32
CPC Classifications
H; H10; H10W; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H10W44/00; H10W44/20; H10W70/00; H10W70/60; H10W70/611; H10W90/00; H10W44/226
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
159 words
A device for connecting in parallel 2n transistor chips (1, 2, 3, 4) for operating at high power and very high frequency, said device comprising: a lower thermally and electrically conducting plate (10), 2n wafers (5, 6, 7, 8) electrically insulating and thermally conductive, welded to said conducting plate (10), arranged in n columns, and on each of which one of said 2n chips is placed, an upper electrically insulating plate (15) supporting two metallized zones (60, 70) on its outer face, said insulating plate facing said conducting plate, and wherein each wafer is provided with at least three terminals (11, 12, 13, 14) respectively connected with each electrode of said one of said 2n transistor chips, one of said terminals (12) being connected with said conducting plate and two of said terminals (11, 14) supporting conducting projections (111) traversing said upper insulating plate and each of said two terminals respectively contacting one of said metallized zones (60, 70).
Claim 2
Independent Claim
159 words
A device for connecting in parallel 2n transistor chips (1, 2, 3, 4) for operating at high power and very high frequency, said device comprising: a lower thermally and electrically conducting plate (10), 2n wafers (5, 6, 7, 8) electrically insulating and thermally conductive, welded to said conducting plate (10), arranged in n columns, and on each of which one of said 2n chips is placed, an upper electrically insulating plate (15) supporting two metallized zones (60, 70) on its outer face, said insulating plate facing said conducting plate, and wherein each wafer is provided with at least three terminals (11, 12, 13, 14) respectively connected with each electrode of said one of said 2n transistor chips, one of said terminals (12) being connected with said conducting plate and two of said terminals (11, 14) supporting conducting projections (111) traversing said upper insulating plate and each of said two terminals respectively contacting one of said metallized zones (60, 70).
Claim 3
Dependent Claim
31 words
A device according to claim 1, wherein said transistors are located in a case, whose base is constituted by said conducting plate and whose cover is constituted by said insulating plate.
Claim 4
Dependent Claim
21 words
A device according to claim 1, wherein said two terminals correspond to the base and the collector of a bipolar transistor.
Claim 5
Dependent Claim
21 words
A device according to claim 1, wherein said two terminals correspond to the gate and the drain of a field-effect transistor.
Claim 6
Dependent Claim
31 words
A device according to claim 1, wherein said transistor chips are made from silicon, the wafers from beryllium oxide and the insulating plate from a ceramic material covered with metal zones.
Claim 7
Dependent Claim
38 words
A device according to claim 2, wherein said insulating plate is provided with a metal coating on its edges so that it can be welded to the border of said case, thereby ensuring the sealing of said case.
References Cited (Backward Citations)
US4296456A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-03 | 1987-04-04 | 1987-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-03 | 1991-04-04 | 1991-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-03 | 1995-04-04 | 1995-10-04 | $7700.00 | Window Closed / Lapsed |