Process for formation of trench in integrated circuit structure using isotropic and anisotropic etching

Claim 2

An improved method for making a trench in an integrated circuit structure wherein voids formed during deposition of material to refill the trench are not opened during planarization whereby oxidation of the walls of the void is prevented, the method comprising: (a) patterning a silicon oxide layer previously deposited on a silicon integrated circuit structure containing device regions to be separated by said trench to form a mask; (b) isotropically etching through said mask a shallow opening in said silicon layer sufficiently to undercut the edges of the openings in said overlying silicon oxide mask; (c) anisotropically etching said silicon through said same mask to the desired depth of the trench; (d) oxidizing the walls of said trench to provide electrical insulation between devices in said integrated circuit structure separated by said trench; (e) refilling the trench by depositing material therein; (f) planarizing said structure to remove any of said material deposited on the surface of said structure adjacent said trench; and (g) growing an oxide layer layer said material in said trench.

Claim 3

The method of claim 1 including the further step of implanting boron into the region of said silicon layer beneath said trench prior to said oxidation.

Claim 4

The method of claim 2 including the step of etching said trench to clean said walls and repair any damage after said anisotropic etching step and removal of said oxide mask.

Claim 5

The method of claim 3 wherein said patterning step includes patterning a layer of nitride positioned between said silicon oxide mask and said silicon layer.

Claim 6

The method of claim 4 including the further step, after said anisotropic step, of removing those portions of said nitride layer above an oxide layer and in between said oxide mask and said silicon which protrude into said shallow opening after said shallow isotropic etching step.

Claim 7

The method of claim 5 including the step of removing said oxide mask before said oxidizing of said trench walls and any depositions in said trench.

Claim 8

The method of claim 6 wherein said material used to refill said trench is polysilicon.

Claim 9

The method of claim 7 including the further step of patterning said nitride layer after said planarization step to permit growing an oxide region between the edge of said trench and adjacent active device regions as well as over said trench.

Claim 10

The method of claim 7 including the further steps of placing a further nitride layer on said structure after said planarization step and patterning said further nitride layer to permit placement of an oxide layer over at least said trench.

Claim 11

The method of claim 7 wherein said isotropic etching step is carried out for a sufficient time to permit said shallow opening to reach a depth of 0.5 to 1.0 microns.

Claim 12

The method of claim 10 wherein said isotropic etching step comprises plasma etching said silicon with SF 6 .

Claim 13

The method of claim 10 wherein said isotropic etching step comprises etching with a chemical etch capable of attacking silicon.

Claim 14

The method of claim 10 wherein said anisotropic etch step uses a reactive ion etch.

Claim 15

The method of claim 13 wherein said anisotropic etch step is carried out for a time period sufficient to provide a trench depth of about 6 microns.

Claim 16

In a process for making an integrated circuit structure wherein a trench is etched into one or more layers to electrically separate one of the devices in the integrated circuit structure from other portions thereof by first patterning a silicon oxide layer which is on a layer of silicon to form a mask, the improvement which comprises: isotropically etching said silicon layer through said mask to provide an enlarged shallow etch area undercutting said patterned silicon oxide mask; whereby subsequent deeper anisotropic etching through the same mask to form said trench will result in a trench having an enlarged upper width to prevent the formation of voids adjacent the upper portion of the trench during subsequent oxidation and polysilicon deposition steps thereby eliminating possible creation of openings to such voids in said polysilicon during subsequent planarization and resultant undesirable oxidation of such voids and undesirable stress formation therefrom.

Claim 17

In a process for making an integrated circuit structure wherein a trench is etched into one or more layers to electrically separate one of the devices in the integrated circuit structure from other portions thereof by first patterning a silicon oxide layer which is on a layer of silicon to form a mask, the improvement which comprises: isotropically etching said silicon layer through said mask to provide an enlarged shallow etch area undercutting said patterned silicon oxide mask; whereby subsequent deeper anisotropic etching through the same mask to form said trench will result in a trench having an enlarged upper width to prevent the formation of voids adjacent the upper portion of the trench during subsequent oxidation and polysilicon deposition steps thereby eliminating possible creation of openings to such voids in said polysilicon during subsequent planarization and resultant undesirable oxidation of such voids and undesirable stress formation therefrom.

Claim 18

The method of claim 15 wherein said isotropic etching step is carried out for a sufficient time to permit said shallow opening to reach a depth of 0.5 to 1.0 microns.

Claim 19

The method of claim 16 wherein said isotropic etching step comprises plasma etching said silicon with SF 6 .

Claim 20

The method of claim 16 wherein said isotropic etching step comprises etching with a chemical etch capable of attacking silicon.

Claim 21

An improved method for making a trench in an integrated circuit structure wherein any voids formed during deposition of polysilicon to refill the trench are not opened during planarization whereby oxidation of the walls of the void is prevented, the method comprising: (a) patterning layers of silicon oxide and silicon nitride previously deposited over a layer of silicon on an integrated circuit structure containing devices to be separated by said trench to form a mask; (b) isotropically etching a shallow opening in said silicon layer through said mask sufficiently to undercut the edges of the openings in said overlying silicon oxide and nitride mask and to provide an opening depth of 0.5 to 1.0 microns; (c) anisotropically etching said silicon through said same mask to the desired depth of the trench; (d) implanting boron into the region of said silicon layer beneath said trench; (e) etching to remove any deposits from the walls of said trench and to remove protruding portions of an oxide layer between said silicon and said silicon nitride layer which protrudes into said shallow opening after said shallow isotropic etching step; (f) chemically etching the walls of said trench to remove any surface damage thereto; (g) removing those portions of said silicon nitride layer which protrude into said shallow opening after said shallow isotropic etching step; (h) removing said oxide mask; (i) oxidizing the walls of said trench to provide electrical insulation between devices in said integrated circuit structure separated by said trench; (j) refilling said trench by depositing silicon therein; (k) planarizing said structure to remove polysilicon deposited on the surface of said structure adjacent said trench; (l) removing those portions of said nitride layer remaining after polishing (m) placing a nitride layer over said polysilicon; (n) patterning said nitride layer to permit placement of an oxide layer at least over said trench; and (o) placing an oxide layer over said material in said trench.

Claim 22

An improved method for making a trench in an integrated circuit structure wherein any voids formed during deposition of polysilicon to refill the trench are not opened during planarization whereby oxidation of the walls of the void is prevented, the method comprising: (a) patterning layers of silicon oxide and silicon nitride previously deposited over a layer of silicon on an integrated circuit structure containing devices to be separated by said trench to form a mask; (b) isotropically etching a shallow opening in said silicon layer through said mask sufficiently to undercut the edges of the openings in said overlying silicon oxide and nitride mask and to provide an opening depth of 0.5 to 1.0 microns; (c) anisotropically etching said silicon through said same mask to the desired depth of the trench; (d) implanting boron into the region of said silicon layer beneath said trench; (e) etching to remove any deposits from the walls of said trench and to remove protruding portions of an oxide layer between said silicon and said silicon nitride layer which protrudes into said shallow opening after said shallow isotropic etching step; (f) chemically etching the walls of said trench to remove any surface damage thereto; (g) removing those portions of said silicon nitride layer which protrude into said shallow opening after said shallow isotropic etching step; (h) removing said oxide mask; (i) oxidizing the walls of said trench to provide electrical insulation between devices in said integrated circuit structure separated by said trench; (j) refilling said trench by depositing silicon therein; (k) planarizing said structure to remove polysilicon deposited on the surface of said structure adjacent said trench; (l) removing those portions of said nitride layer remaining after polishing (m) placing a nitride layer over said polysilicon; (n) patterning said nitride layer to permit placement of an oxide layer at least over said trench; and (o) placing an oxide layer over said material in said trench.