Patent US4638498A successfully refreshed from Google Patents.
US4638498A
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Digital timing system
Assignee: Intersil Corp
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Filing: 1985-09-27
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Granted: 1987-01-20
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Expires: 2005-09-27
Abstract
Abstract A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations each storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter.
Inventors
- 👤 Joseph O. Sinniger
- 👤 Anthony D. Robbi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:53
CPC Classifications
F; F02; F02P; F02P5/00; F02P5/04; F02P5/145; F02P5/15; F02P5/1502; F02P5/1514; Y; Y02; Y02T; Y02T10/00; Y02T10/10; Y02T10/40
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
97 words
A system for producing an output pulse at a time which is a function of the spacing of two input pulses, comprising a source of clock pulses, a counter connected to count the number of clock pulses occurring in the period between said two input pulses, a source of an addend quantity, adder/accumulator means responsive to said source of clock pulses and to said source of an addend quantity to repeatedly add said addend quantity, and a comparator producing an output pulse when the sum provided by said adder/accumulator corresponds with the counted number of clock pulses.
Claim 2
Independent Claim
97 words
A system for producing an output pulse at a time which is a function of the spacing of two input pulses, comprising a source of clock pulses, a counter connected to count the number of clock pulses occurring in the period between said two input pulses, a source of an addend quantity, adder/accumulator means responsive to said source of clock pulses and to said source of an addend quantity to repeatedly add said addend quantity, and a comparator producing an output pulse when the sum provided by said adder/accumulator corresponds with the counted number of clock pulses.
Claim 3
Independent Claim
136 words
A system for producing an output pulse at a time which is a function of the spacing of two input pulses, comprising a source of clock pulses, a counter connected to count and latch the number of clock pulses occurring in the period between said two input pulses, a memory having memory locations storing addend quantities and corresponding repeats numbers, adder/accumulator means operative after said count is latched to access said memory and add said addend quantities a number of times determined by corresponding repeats numbers, and a comparator producing an output pulse when the sum provided by said adder/accumulator corresponds with the latched count in said counter, said addend quantities and repeats numbers in said memory being selected so that said output pulse occurs at a time dependent on the spacing of the input pulses.
Claim 4
Independent Claim
136 words
A system for producing an output pulse at a time which is a function of the spacing of two input pulses, comprising a source of clock pulses, a counter connected to count and latch the number of clock pulses occurring in the period between said two input pulses, a memory having memory locations storing addend quantities and corresponding repeats numbers, adder/accumulator means operative after said count is latched to access said memory and add said addend quantities a number of times determined by corresponding repeats numbers, and a comparator producing an output pulse when the sum provided by said adder/accumulator corresponds with the latched count in said counter, said addend quantities and repeats numbers in said memory being selected so that said output pulse occurs at a time dependent on the spacing of the input pulses.
Claim 5
Independent Claim
100 words
A system for producing an output pulse at a time which is a function of the duration ΔA of the time interval between two input pulses, comprising a source of clock pulses, a counter connected to count the number of clock pulses occurring during a time interval of duration ΔA, a source of an addend quantity, adder/accumulator means responsive to said source of clock pulses and to said source of addend quantity to repeatedly add said addend quantity, and a comparator producing an output pulse when the sum provided by said adder/accumulator corresponds with the counted number of clock pulses.
Claim 6
Independent Claim
100 words
A system for producing an output pulse at a time which is a function of the duration ΔA of the time interval between two input pulses, comprising a source of clock pulses, a counter connected to count the number of clock pulses occurring during a time interval of duration ΔA, a source of an addend quantity, adder/accumulator means responsive to said source of clock pulses and to said source of addend quantity to repeatedly add said addend quantity, and a comparator producing an output pulse when the sum provided by said adder/accumulator corresponds with the counted number of clock pulses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-19 | 1990-07-21 | 1991-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-19 | 1994-07-21 | 1995-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-19 | 1998-07-21 | 1999-01-20 | $7700.00 | Window Closed / Lapsed |