Patent US4638460A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4638460A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: Hitachi Ltd
•
Filing: 1983-09-07
•
Granted: 1987-01-20
•
Expires: 2003-09-07
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor memory device is provided with memory cells which each comprises an insulated gate type field effect transistor and a capacitor connected in series with one another and connected to bit lines. The capacitor is composed of a pair of electrodes and a dielectric film which includes a silicon nitride film existing between the pair of electrodes. One electrode of the capacitor is provided with a terminal to which a voltage is applied. The value of the applied voltage is chosen so that the voltage applied between the pair of electrodes is smaller in an absolute value than a voltage applied to the bit line.

Inventors

  • 👤 Tetsuro Matsumoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 17:49
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00; H10B12/30; H10D; H10D84/00

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 156 words
A semiconductor memory device comprising: a memory cell which includes a series connection comprised of a switching MISFET and a storage capacitor connected in series, said storage capacitor being comprised of a semiconductor region of a semiconductor substrate, a silicon nitride film formed over a surface of said semiconductor region, and a conductive layer formed over said silicon nitride film; a bit line which is connected to one end of said series connection and which supplies a signal voltage having a predetermined maximum value to said memory cell; and a terminal which is connected to the other end of said series connection and which supplies a voltage to said other end of said series connection so that a voltage of said storage capacitor to be stored between said semicoductor region and said conductive layer has a smaller absolute value than an absolute value of said maximum value of said signal voltage supplied to said bit line.
Claim 2
Dependent Claim 156 words
A semiconductor memory device comprising: a memory cell which includes a series connection comprised of a switching MISFET and a storage capacitor connected in series, said storage capacitor being comprised of a semiconductor region of a semiconductor substrate, a silicon nitride film formed over a surface of said semiconductor region, and a conductive layer formed over said silicon nitride film; a bit line which is connected to one end of said series connection and which supplies a signal voltage having a predetermined maximum value to said memory cell; and a terminal which is connected to the other end of said series connection and which supplies a voltage to said other end of said series connection so that a voltage of said storage capacitor to be stored between said semicoductor region and said conductive layer has a smaller absolute value than an absolute value of said maximum value of said signal voltage supplied to said bit line.
Claim 3
Dependent Claim 27 words
A semiconductor memory device according to claim 1, wherein said silicon nitride film is formed on a silicon oxide film which is formed on said semiconductor region.
Claim 4
Dependent Claim 25 words
A semiconductor memory device according to claim 1, wherein a voltage substantially equal to half of said maximum signal voltage is applied to said terminal.
Claim 5
Dependent Claim 25 words
A semiconductor memory device according to claim 2, wherein a voltage substantially equal to half of said maximum signal voltage is applied to said terminal.
Claim 6
Dependent Claim 175 words
A semiconductor memory device comprising: a memory cell which includes a series connection comprised of a switching MISFET and a storage capacitor connected in series, said storage capacitor being comprised of a semiconductor region of a semiconductor substrate, a silicon nitride film formed over a surface of said semiconductor region, and a conductive layer formed over said silicon nitride film; a bit line which is connected to one end of said series connection and which supplies a signal voltage having a predetermined high level V H and a predetermined low level V L to said memory cell; and a terminal which is connected to the other end of said series connection and which supplied a voltage V P which is greater than V L but less than V H to said other end of said series connection so that a voltage V S of said storage capacitor to be stored between said semiconductor region and said conductive layer has a smaller absolute value than the absolute value of V H supplied to said bit line.
Claim 7
Dependent Claim 175 words
A semiconductor memory device comprising: a memory cell which includes a series connection comprised of a switching MISFET and a storage capacitor connected in series, said storage capacitor being comprised of a semiconductor region of a semiconductor substrate, a silicon nitride film formed over a surface of said semiconductor region, and a conductive layer formed over said silicon nitride film; a bit line which is connected to one end of said series connection and which supplies a signal voltage having a predetermined high level V H and a predetermined low level V L to said memory cell; and a terminal which is connected to the other end of said series connection and which supplied a voltage V P which is greater than V L but less than V H to said other end of said series connection so that a voltage V S of said storage capacitor to be stored between said semiconductor region and said conductive layer has a smaller absolute value than the absolute value of V H supplied to said bit line.
Claim 8
Dependent Claim 16 words
A semiconductor memory device according to claim 5, wherein V P =V H +V L /2.

References Cited (Backward Citations)

US4322881A Cited
US4456978A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-01-19 1990-07-21 1991-01-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-01-19 1994-07-21 1995-01-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-01-19 1998-07-21 1999-01-20 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag