Semiconductor memory address lines with varied interval contact holes

Claim 1

A semiconductor memory device comprising: (a) a semiconductor substrate; (b) a plurality of memory cells, which are formed on said semiconductor substrate, each having a memory cell transistor and a memory cell capacitor which is charged so as to reflect the logic state of its memory cell; and (c) address lines which extend in row and column directions on said semiconductor substrate and select a particular memory cell for reading/writing data from/in the desired memory cell, said address lines including double layered address lines each of which comprises, (i) first and second conductive lines of linear shapes each of which has a first end portion for receiving a voltage signal for selecting the particular memory cell and a second end portion at an opposite side of said first end portion, which are stacked, and which extend in one of the row and column directions, and (ii) a linear insulative layer which extends along an extending direction of said first and second conductive lines, is sandwiched between said first and second conductive lines, has contact holes formed along the extending direction of said first and second conductive lines, and allows electrical connection between said first and second conductive lines through the contact holes, an interval of two neighbouring contact holes at the second end portion of each of said first and second conductive lines being set to be smaller than that of two neighbouring contact holes at the first end portion of each of said first and second conductive lines, thereby decreasing the maximum delay time in signal transfer at the second end portion of each of said double layered address lines, and the interval between two neighbouring contact holes at the first end portion of each of said first and second conductive lines is increased, thereby avoiding an increase in the total number of contact holes.