Storage of digitized video images on disk

Claim 1

A digital data deskewing circuit for use with a parallel transfer digital disk drive having a plurality of coaxially arranged magnetic disks rotating together at a constant speed, a plurality of digital data transmission channels and read/write heads magnetically coupling the channels to the disks, respectively, a master clock controlling writing on the respective disks a number of digital words, bytes or other digital data bit groups, said groups being written on each disk as a serial stream of bits, during reading of the streams from the disks said drive providing a bit read clock pulse train for each channel for defining the bits and a sync data bit grouping derived from the disk and preceding valid digital data, said clock pulses sometimes being out of synchronism with each other such that the data bits are skewed in time relative to each other during readout of the disks, said disk drive issuing an index pulse for each disk revolution sectors pulses marking each disk sector, deskewing circuit means comprising master sequencer means referenced to the index and sector time base of the disk drive and operative to provide clock pulse signals for serial bit stream outputs from all channels at the same time, each channel including serial-to-parallel converter means having a data input for serial bits from a disk and an input for said bit read clock of the channel, said converter having a predetermined number of parallel bit outputs, sync detector means coupled to said parallel bit outputs of said converter means, detection of said sync data indicating that serial bits composing valid data follow, digital latch means having parallel bit inputs coupled to the respective parallel bit outputs of said converter means and having corresponding outputs and a clock pulse input which clock rate is a fraction of the bit read clock rate to said serial-to-parallel converter, so that for every latch means clock said predetermined number of bits will be transferred from said converter to said latch means, first-in, first-out (FIFO) memory means having parallel bit inputs coupled to corresponding outputs of said latch means, having corresponding parallel bit outputs and having an input clock that is such fraction of said read clock rate and having an output clock supplied by said master sequencer means for controlling the rate at which parallel bits are transferred together out of said FIFO memory means, parallel-to-serial converter means having parallel bit inputs coupled to corresonding outputs of said FIFO memory means and having a bit rate output control clock supplied by said master sequencer and having an output for serially arranged bits, and another sequencer means with its input coupled to said sync detector means and responding to detection of said sync data by initiating control and clocking of said latch means and FIFO memory means to transfer said predetermined number of parallel bits per clock pulse.