Patent US4638261A successfully refreshed from Google Patents.
US4638261A
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US
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Low noise amplifier with high intercept point
Assignee: Unisys Corp
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Filing: 1985-08-26
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Granted: 1987-01-20
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Expires: 2005-08-26
Abstract
Abstract A low noise amplifier (LNA) circuit including a linear amplifier which generates low noise in the presence of a high level signal and includes a field effect transistor with input and output matching networks and which retains linear operation in the presence of high level (high magnitude) interfering signals.
Inventors
- 👤 Charles F. McGuire
- 👤 Gordon C. Steyaert
- 👤 John M. Fontaine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:05
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H03F3/193; H03F3/1935; H03F3/60; H03F3/601; H03F2200/00; H03F2200/294; H03F2200/372
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
112 words
A low noise, high intercept point, single ended, linear amplifier comprising, a field effect transistor including a gate electrode, a source electrode and a drain electrode, said transistor having large gate width parameters on the order of 3000 microns, a gate matching network comprising a distributed dispersive media connected to the gate electrode of said transistor to present a standard noise match to said gate electrode thereby to achieve a minimum noise factor for said amplifier, and a drain matching network comprising a distributed dispersive media connected to the drain electrode of said transistor in order to provide the optimal power load for said transistor thereby to achieve a high intercept point.
Claim 2
Dependent Claim
112 words
A low noise, high intercept point, single ended, linear amplifier comprising, a field effect transistor including a gate electrode, a source electrode and a drain electrode, said transistor having large gate width parameters on the order of 3000 microns, a gate matching network comprising a distributed dispersive media connected to the gate electrode of said transistor to present a standard noise match to said gate electrode thereby to achieve a minimum noise factor for said amplifier, and a drain matching network comprising a distributed dispersive media connected to the drain electrode of said transistor in order to provide the optimal power load for said transistor thereby to achieve a high intercept point.
Claim 3
Dependent Claim
19 words
The amplifier recited in claim 1 including, bond wires connecting said media to the gate electrode of said FET.
Claim 4
Dependent Claim
14 words
The amplifier recited in claim 1 wherein, said gate matching network comprises micro stripline.
Claim 5
Dependent Claim
14 words
The amplifier recited in claim 1 wherein, said gate matching network comprises open strip.
Claim 6
Dependent Claim
163 words
An amplifying system which exhibits low noise, high intercept points and maximum power, comprising at least one low noise, high intercept point, single ended, and linear amplifier circuit including, a field effect transistor including a gate electrode, a source electrode and a drain electrode, said transistor having large gate width parameters on the order of 3000 microns, a gate matching network comprising a distributed dispersive media connected to the gate electrode of said transistor to present a standard noise match to said gate electrode thereby to achieve a minimum noise factor for said amplifier, a drain matching network comprising a distributed dispersive media connected to the drain electrode of said transistor so as to thereby provide the optimal power load for said transistor thereby to achieve high intercept point operation, input load means connected to an input of said amplifier circuit at said gate matching network, and output load means connected to an output of said amplifier circuit at said drain matching network.
Claim 7
Dependent Claim
163 words
An amplifying system which exhibits low noise, high intercept points and maximum power, comprising at least one low noise, high intercept point, single ended, and linear amplifier circuit including, a field effect transistor including a gate electrode, a source electrode and a drain electrode, said transistor having large gate width parameters on the order of 3000 microns, a gate matching network comprising a distributed dispersive media connected to the gate electrode of said transistor to present a standard noise match to said gate electrode thereby to achieve a minimum noise factor for said amplifier, a drain matching network comprising a distributed dispersive media connected to the drain electrode of said transistor so as to thereby provide the optimal power load for said transistor thereby to achieve high intercept point operation, input load means connected to an input of said amplifier circuit at said gate matching network, and output load means connected to an output of said amplifier circuit at said drain matching network.
Claim 8
Dependent Claim
38 words
The system recited in claim 5 including, a pair of said amplifier circuits connected by means of Lange-type quadrature couplers in order to balance said pair of amplifier circuits and to produce good input and output reflection coefficients.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-19 | 1990-07-21 | 1991-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-19 | 1994-07-21 | 1995-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-19 | 1998-07-21 | 1999-01-20 | $7700.00 | Window Closed / Lapsed |