US4636823A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vertical Schottky barrier gate field-effect transistor in GaAs/GaAlAs
Assignee: California Institute of Technology
•
Filing: 1984-06-05
•
Granted: 1987-01-13
•
Expires: 2004-06-05
Abstract
Abstract High transconductance vertical FETs are produced in III-V epitaxially grown layers doped n, p and n, with the in-between submicron (0.15 μm) layer serving as the FET channel. The layer on the drain side of the channel may be thicker (3 μm) than on the source side (1.5 μm). The structure is V-grooved to expose a nearly vertical surface that is Si implanted or regrown with graded n-type GaAs/GaAlAs before a gate contact is deposited on the vertical structure. An alternative to employ a heterostructure with GaAlAs layers for the source and drain, and GaAs for the channel layer. Graded GaAs/GaAlAs is then selectively regrown in the channel layer.
Inventors
- 👤 Shlomo Margalit
- 👤 Amnon Yariv
- 👤 Zeev Rav-Noy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D30/871; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
106 words
A vertical field-effect transistor comprised of epitaxial layers of III-V semiconductor material including a drain layer grown more than one micron thick, a channel layer, and a source layer grown more than one micron thick, with said channel layer grown between said source and drain layers to a controlled submicron thickness for high transconductance of the transistor, and have exposed a cross sectional surface through said channel layer,and further including source and drain contacts for respective one of said source and drain layers, and means for providing a depletion layer of a Schottky barrier gate on the exposed cross sectional surface of said submicron channel layer.
Claim 2
Dependent Claim
106 words
A vertical field-effect transistor comprised of epitaxial layers of III-V semiconductor material including a drain layer grown more than one micron thick, a channel layer, and a source layer grown more than one micron thick, with said channel layer grown between said source and drain layers to a controlled submicron thickness for high transconductance of the transistor, and have exposed a cross sectional surface through said channel layer,and further including source and drain contacts for respective one of said source and drain layers, and means for providing a depletion layer of a Schottky barrier gate on the exposed cross sectional surface of said submicron channel layer.
Claim 3
Dependent Claim
26 words
A vertical field-effect transistor as defined in claim 1 wherein said source and drain layers are n-type GaAs layers, and said channel layer is p-type GaAs.
Claim 4
Dependent Claim
88 words
A vertical field-effect transistor as defined in claim 1 wherein said three epitaxial layers are grown on a GaAs substrate with a GaAs channel layer between said source and drain layers, and said means is comprised of silicon implanted in said channel layer through said exposed vertical surface to provide the depletion layer of a Schottky barrier gate on the channel layer, whereby modulation of the depletion region in the channel layer with a signal applied on said gate will control conduction between said source and drain contacts.
Claim 5
Dependent Claim
64 words
A vertical field-effect transistor as defined in claim 1 wherein said three epitaxial layers are grown on n+GaAs substrate with a p-type GaAs channel layer in between n-type GaAs source and drain layers, and said means is comprised of graded n-type GaAs/GaAlAs regrown on said exposed cross sectional surface to provide the depletion layer of a Schottky barrier gate on the p-type channel layer.
Claim 6
Dependent Claim
76 words
A vertical field-effect transistor as defined in claim 1 wherein said three epitaxial layers are grown on n + GaAs substrate with a p-type GaAs channel layer in between n-type Ga 1-x Al x As source and drain layers, and said means is comprised of n-type graded GaAs/GaAlAs preferentially regrown on the exposed cross sectional surface of said p-type channel layer to provide the depletion layer of a Schottky barrier gate on the p-type channel layer.
Claim 7
Dependent Claim
26 words
A vertical field-effect transistor as defined in claim 3 wherein said source and drain layers are n-type GaAs layers, and said channel layer is p-type GaAs.
Claim 8
Dependent Claim
142 words
A high transconductance vertical field-effect transistor comprising epitaxially grown layers of GaAs semiconductor material grown on a substrate of said material doped n + , a first thick layer of about 3 μm in thickness of said material n doped about 1.5×10 17 cm -3 , a second thin layer about 0.15 μm in thickness of said material p doped from 1 to 2×10 17 cm -3 , and a third layer about 1.5 μm in thickness of said material n doped about 3×10 17 cm -3 , a groove of about 2.5 μm depth to expose in a cross sectional surface said second thin layer, source and drain contacts for respective ones of said third layer and substrate, and means for providing a depletion region of a Schottky barrier gate on said exposed cross sectional surface of said second, thin layer.
Claim 9
Dependent Claim
142 words
A high transconductance vertical field-effect transistor comprising epitaxially grown layers of GaAs semiconductor material grown on a substrate of said material doped n + , a first thick layer of about 3 μm in thickness of said material n doped about 1.5×10 17 cm -3 , a second thin layer about 0.15 μm in thickness of said material p doped from 1 to 2×10 17 cm -3 , and a third layer about 1.5 μm in thickness of said material n doped about 3×10 17 cm -3 , a groove of about 2.5 μm depth to expose in a cross sectional surface said second thin layer, source and drain contacts for respective ones of said third layer and substrate, and means for providing a depletion region of a Schottky barrier gate on said exposed cross sectional surface of said second, thin layer.
Claim 10
Dependent Claim
47 words
A vertical field-effect transistor as defined in claim 7 wherein said means is comprised of silicon implanted in said thin, second layer through said exposed cross sectional surface to provide the depletion layer of a Schottky barrier gate, and a metal contact deposited over said implanted silicon.
Claim 11
Dependent Claim
44 words
A vertical field-effect transistor as defined in claim 7 wherein said means is comprised of graded n-type GaAs/GaAlAs grown over said exposed cross sectional surface to provide the depletion layer of a Schottky barrier gate, and a metal contact deposited over said graded GaAs/GaAlAs.
Claim 12
Dependent Claim
162 words
A high transconductance vertical field-effect transistor comprising epitaxially grown layers of GaAs and GaAlAs semiconductor materials grown on a substrate of said n+GaAs, a first thick layer about 3 μm in thickness of GaAlAs n doped about 1.5×10 17 cm -3 , a second, thin layer about 0.15 μm in thickness of GaAs p doped from 1 to 2×10 17 cm -3 , and a third layer about 1.5 μm in thickness of GaAlAs material in doped about 3×10 17 cm -3 ; a groove of about 2.5 μm depth to expose a cross sectional surface of said second layer, source and drain contacts for respective ones of said third layer and substrate, and means for providing a Schottky barrier gate in the exposed cross sectional surface of said second layer comprised of graded n-type GaAs/GaAlAs selectively regrown over the exposed cross sectional surface of said second layer in said groove and a metal contact deposited over said graded GaAs/GaAlAs selectively regrown.
Claim 13
Dependent Claim
162 words
A high transconductance vertical field-effect transistor comprising epitaxially grown layers of GaAs and GaAlAs semiconductor materials grown on a substrate of said n+GaAs, a first thick layer about 3 μm in thickness of GaAlAs n doped about 1.5×10 17 cm -3 , a second, thin layer about 0.15 μm in thickness of GaAs p doped from 1 to 2×10 17 cm -3 , and a third layer about 1.5 μm in thickness of GaAlAs material in doped about 3×10 17 cm -3 ; a groove of about 2.5 μm depth to expose a cross sectional surface of said second layer, source and drain contacts for respective ones of said third layer and substrate, and means for providing a Schottky barrier gate in the exposed cross sectional surface of said second layer comprised of graded n-type GaAs/GaAlAs selectively regrown over the exposed cross sectional surface of said second layer in said groove and a metal contact deposited over said graded GaAs/GaAlAs selectively regrown.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-12 | 1990-07-14 | 1991-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-12 | 1994-07-14 | 1995-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-12 | 1998-07-14 | 1999-01-13 | $7700.00 | Window Closed / Lapsed |