Field effect transistor

Claim 2

A vertical field effect transistor comprising: a semiconductor body; vertically displaced source and drain regions formed in said semiconductor body; an insulating layer disposed between and separating said source and drain regions; said source region, said drain region and said insulating layer all extend to a common edge surface; a thin conductive layer formed on said edge surface so that it bridges said insulating layer, and directly contacts the edge surface of said source and drain regions; a rectifying metal/semiconductor gate contact on said thin conductive semiconductor layer; a drain contact for said drain region; and a source contact for said source region.

Claim 3

A field effect transistor as defined in claim 1, wherein said thin conductive layer comprises a semiconductor layer produced epitaxially, by diffusion or by ion implantation.

Claim 4

A field effect transistor as defined in claim 1, wherein said insulating layer is produced by ion implantation so deeply beneath the semiconductor surface that a semiconductor region which forms said source or said drain region remains at the surface of said semiconductor body.

Claim 5

A field effect transistor as defined in claim 1, wherein said insulating layer is a thin layer arranged in said semiconductor body between a thin, conducting surface region, which is of a predetermined type of conductivity and forms said source region, and the substrate, which is of the same type of conductivity and forms said drain region, a V-shaped depression is formed in one major surface of said semiconductor body and penetrates said surface region and said insulating layer and extends into said substrate, whereby one side of said groove forms said common edge surface; said thin conductive layer is a semiconductor layer arranged in said depression; and said gate contact is a Schottky contact applied to said thin conductive layer within said depression.

Claim 6

A field effect transistor as defined in claim 1 wherein: a mesa-type semiconductor elevation is arranged on a major surface of a semiconductor substrate, which forms said source region, to provide said semiconductor body; said insulating layer is a thin layer arranged within said mesa elevation beneath a surface region which is disposed at the top of said mesa elevation and forms said drain region; said thin conductive layer is located on the side surface of said mesa elevation and connects said source region to said drain region whereby said side surface forms said common edge surface; and said gate contact is a Schottky contact applied to said thin conductive layer bridging said insulating layer on said side surface of said mesa elevation.

Claim 7

A field effect transistor as defined in claim 1, wherein said conductive layer is approximately 0.1 μm thick for the purpose of forming a self-blocking transistor and has an impurity concentration of approximately 10 16 atoms/cm 3 .

Claim 8

A field effect transistor as defined in claim 1, wherein said conductive layer is approximately 0.2 μm thick for the purpose of forming a self-conducting transistor and has an impurity concentration of approximately 10 17 atoms/cm 3 .

Claim 9

A field effect transistor as defined in claim 1, wherein said insulating layer is arranged approximately 0.3 to 0.5 μm beneath the semiconductor surface.

Claim 10

A field effect transistor according to claim 1, wherein said insulating layer is approximately 0.1 to 0.3 μm thick.

Claim 11

A field effect transistor as defined in claim 1, wherein said gate electrode extends onto a relatively thick insulating layer arranged on a major surface of said semiconductor body.

Claim 12

A vertical field effect transistor as defined in claim 1 wherein said source and drain regions and said insulating layer are all planar.

Claim 13

A vertical field effect transistor as defined in claim 1 wherein said source region, said drain region and said thin conductive region are all semiconductor regions of the same conductivity type.

Claim 14

A field effect transistor as defined in claim 4 wherein said source region, said drain region and said thin conductive layer are all of the same conductivity type.