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JPS5524433A Expired / Lapsed JP ⏱️ 0.0 years remaining

Composite type semiconductor device

Assignee: Mitsubishi Electric Corp
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Filing: 1978-08-09
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Granted: —
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Expires: 1998-08-09
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Abstract

Abstract PURPOSE: To facilitate coexistence with enhancement (E) type FET or formation of EE type composite IC by controlling threshold voltage through injecting ion in the channel of depletion (D) type FET. CONSTITUTION: P layer 114 is formed through placing P - epitaxial layer on P layer 110 having N + embedded layer 111 with its one end 113 kept right above the layer 111 and the other end 115 left from prividing N + layer 116 shallowly. Next, V channel is formed to reach the embedded layer and covered with a field insulating film 123. There may be formed P or N type ion-impregnated layer 124, where preferable, on P layer 112 at slope 121 side. There are further provided a source electrode 127, drain electrode 130 through the insulating film 123, gate electrodes 128, 129 on the slope and an electrode 132 on the channel bottom. According to this constitution, an inverter of ED or EE type can be formed in one opening by setting Vth of one side FET at an arbitrary value through controlling conduction type and specific resistance of the ion-impregnated layer 124 under the circumstances prevailing then. COPYRIGHT: (C)1980,JPO&Japio

Inventors

  • 👤 Hideyuki Ozaki
  • 👤 Kazuhiro Shimotori
  • 👤 Yasuharu Nagayama

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 19:17
CPC Classifications
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