Patent US4636773A successfully refreshed from Google Patents.
US4636773A
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Binarily weighted pulse width digital-to-analog converter
Assignee: Raytheon Co
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Filing: 1985-11-25
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Granted: 1987-01-13
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Expires: 2005-11-25
Abstract
Abstract A digital-to-analog converter system for converting a digital input signal having parallel words, each word including multi-bit groups of weighted significance, and which is provided at an input word rate of W Hz, is disclosed. The digital-to-analog converter system (10, 100, 200) includes pulse generating circuitry (11, 13, 111, 113, 211, 213) responsive to a first multi-bit group and a second multi-bit group of the digital input words for providing (a) a first pulse modulated signal as a function of the value of the first multi-bit group and (b) a second pulse modulated signal as a function of the value of the second multi-bit group; weighting elements (15, 19, 115, 119, 215, 219) for weighting the first and second pulse modulated signals as a function of the relative weighted significance of the first and second multi-bit groups; and output circuitry (20, 120, 220) for summing and filtering the weighted signals to provide an analog output signal that is representative of the digital input signal.
Inventors
- 👤 Dan E. Lewis
- 👤 James L. Gundersen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:01
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/68; H03M1/682; H03M1/82; H03M1/822
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
239 words
A digital-to-analog converter for converting a digital input signal having parallel words, each word including a sign bit and N magnitude bits which include multi-bit groups of weighted significance, and which is provided at an input word rate of W Hz, comprising: pulse generating means responsive to the sign bit and to a first and a second multi-bit group of the N magnitude bits for providing (a) a first pulse modulated signal having pulse widths and levels as a function of the sign bit and the value of the first multi-bit group and (b) a second pulse modulated signal having pulse widths and levels as a function of the sign bit and the value of the second multi-bit group, said first pulse modulated signal including a first predetermined pulse for a first value of the sign bit or a second predetermined pulse for a second value of the sign bit; means for weighting said first and second pulse modulated signals as a function of the relative weighted significance of the first and second multi-bit groups; and means for summing and filtering said weighted signals to provide an analog output signal which as a result of said first and second predetermined pulses includes distinct outputs for (a) an input word having said first sign bit value and magnitude bits that are all 0's and (b) an input word having said second sign bit and magnitude bits that are all 0's.
Claim 2
Dependent Claim
239 words
A digital-to-analog converter for converting a digital input signal having parallel words, each word including a sign bit and N magnitude bits which include multi-bit groups of weighted significance, and which is provided at an input word rate of W Hz, comprising: pulse generating means responsive to the sign bit and to a first and a second multi-bit group of the N magnitude bits for providing (a) a first pulse modulated signal having pulse widths and levels as a function of the sign bit and the value of the first multi-bit group and (b) a second pulse modulated signal having pulse widths and levels as a function of the sign bit and the value of the second multi-bit group, said first pulse modulated signal including a first predetermined pulse for a first value of the sign bit or a second predetermined pulse for a second value of the sign bit; means for weighting said first and second pulse modulated signals as a function of the relative weighted significance of the first and second multi-bit groups; and means for summing and filtering said weighted signals to provide an analog output signal which as a result of said first and second predetermined pulses includes distinct outputs for (a) an input word having said first sign bit value and magnitude bits that are all 0's and (b) an input word having said second sign bit and magnitude bits that are all 0's.
Claim 3
Dependent Claim
120 words
The digital-to-analog converter of claim 1 wherein said pulse generating means comprises: modulation means responsive to the first and second multi-bit groups for providing (a) a first intermediate pulse width modulated signal having widths determined by the first multi-bit group and (b) a second intermediate pulse width modulated signal having widths determined by the second multi-bit group; and switching means responsive to the sign bit and said first and second intermediate pulse width modulated signals for providing (a) said first pulse modulated signal as a function of the sign bit and said first intermediate pulse width modulated signal and (b) said second pulse modulated signal as a function of the sign bit and said second intermediate pulse width modulated signal.
Claim 4
Dependent Claim
129 words
The digital-to-analog converter of claim 2 wherein said modulation means comprises: counting means responsive to a clock signal for providing an output count; logic means responsive to said counting means for providing a pulse clock signal having a frequency of P Hz and defining pulse intervals; first comparison means responsive to the first multi-bit group of the N magnitude bits, said output count, and said pulse clock signal for providing said first intermediate pulse width modulated signal which includes a modulated pulse width during each pulse interval; and second comparison means responsive to the second multi-bit group of the N magnitude bits, said output count, and said pulse clock signal for providing said second intermediate pulse width modulated signal which includes a modulated pulse width during each pulse interval.
Claim 5
Dependent Claim
34 words
The digital-to-analog converter of claim 3 wherein each of the first and second multi-bit groups includes M bits and said clock signal for said counting means has a clock frequency of P×2 M Hz.
Claim 6
Dependent Claim
125 words
The digital-to-analog converter of claim 3 wherein said switching means comprises: first level shifting means responsive to the sign bit and said first intermediate pulse width modulated signal for providing said first pulse modulated signal which includes during each pulse interval said first or second predetermined pulse and a modulated pulse having a width controlled by said first intermediate signal and a level that is a function of the sign bit; and second level shifting means responsive to the sign bit and said second intermediate pulse width modulated signal for providing said second pulse modulated signal which includes during each pulse interval a modulated pulse having a width controlled by said second intermediate signal and a level that is a function of the sign bit.
Claim 7
Dependent Claim
12 words
The digital-to-analog converter of claim 4 wherein N is two times M.
Claim 8
Dependent Claim
179 words
A digital-to-analog converter for converting a digital input signal having parallel words, each word including a sign bit and N magnitude bits which include multi-bit groups of weighted significance, and which is provided at an input word rate of W Hz, comprising: pulse generating means responsive to the sign bit and to a first and a second multi-bit group of the N magnitude bits for providing (a) a first pulse modulated signal having pulse widths and levels as a function of the sign bit and the value of the first multi-bit group and (b) a second pulse modulated signal having pulse widths and levels as a function of the sign bit and the value of the second multi-bit group, said pulse generating means further compensating different transition times of said second pulse modulated signal from one level to another; means for weighting said first and second pulse modulated signals as a function of the relative weighted significance of the first and second multi-bit groups; and means for summing and filtering said weighted signals to provide an analog output signal.
Claim 9
Dependent Claim
179 words
A digital-to-analog converter for converting a digital input signal having parallel words, each word including a sign bit and N magnitude bits which include multi-bit groups of weighted significance, and which is provided at an input word rate of W Hz, comprising: pulse generating means responsive to the sign bit and to a first and a second multi-bit group of the N magnitude bits for providing (a) a first pulse modulated signal having pulse widths and levels as a function of the sign bit and the value of the first multi-bit group and (b) a second pulse modulated signal having pulse widths and levels as a function of the sign bit and the value of the second multi-bit group, said pulse generating means further compensating different transition times of said second pulse modulated signal from one level to another; means for weighting said first and second pulse modulated signals as a function of the relative weighted significance of the first and second multi-bit groups; and means for summing and filtering said weighted signals to provide an analog output signal.
Claim 10
Dependent Claim
17 words
The digital-to-analog converter of claim 7 wherein said second pulse modulated signal includes a predetermined fixed pulse.
Claim 11
Dependent Claim
120 words
The digital-to-analog converter of claim 8 wherein said pulse generating means comprises: modulation means responsive to the first and second multi-bit groups for providing (a) a first intermediate pulse width modulated signal having widths determined by the first multi-bit group and (b) a second intermediate pulse width modulated signal having widths determined by the second multi-bit group; and switching means responsive to the sign bit and said first and second intermediate pulse width modulated signals for providing (a) said first pulse modulated signal as a function of the sign bit and said first intermediate pulse width modulated signal and (b) said second pulse modulated signal as a fumction of the sign bit and said second intermediate pulse width modulated signal.
Claim 12
Dependent Claim
129 words
The digital-to-analog converter of claim 9 wherein said modulation means comprises: counting means responsive to a clock signal for providing an output count; logic means responsive to said counting means for providing a pulse clock signal having a frequency of P Hz and defining pulse intervals; first comparison means responsive to the first multi-bit group of the N magnitude bits, said output count, and said pulse clock signal for providing said first intermediate pulse width modulated signal which includes a modulated pulse width during each pulse interval; and second comparison means responsive to the second multi-bit group of the N magnitude bits, said output count, and said pulse clock signal for providing said second intermediate pulse width modulated signal which includes a modulated pulse width during each pulse interval.
Claim 13
Dependent Claim
34 words
The digital-to-analog converter of claim 10 wherein each of the first and second multi-bit groups includes M bits and said clock signal for said counting means has a clock frequency of P×2 M Hz.
Claim 14
Dependent Claim
123 words
The digital-to-analog converter of claim 10 wherein said switching means comprises: first level shifting means responsive to the sign bit and said first intermediate pulse width modulated signal for providing said first pulse modulated signal which includes during each pulse interval a modulated pulse having a width controlled by said first intermediate signal and a level that is a function of the sign bit; and second level shifting means responsive to the sign bit and said second intermediate pulse width modulated signal for providing said second pulse modulated signal which includes during each pulse interval said predetermined fixed pulse and a modulated pulse having a width controlled by said second intermediate signal and a level that is a function of the sign bit.
Claim 15
Dependent Claim
12 words
The digital-to-analog converter of claim 11 wherein N is two times M.
References Cited (Backward Citations)
US3823396A
Cited
US4016558A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-12 | 1990-07-14 | 1991-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-12 | 1994-07-14 | 1995-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-12 | 1998-07-14 | 1999-01-13 | $7700.00 | Window Closed / Lapsed |