Low spurious numerically controlled oscillator apparatus and method

Claim 2

Low spurious numerically controlled oscillator apparatus comprising: a numerically controlled oscillator having a clock input, a frequency select input and an output, the output having an output signal thereon at a selected frequency defined by a signal on the frequency select input and with a periodically irregular duty cycle for at least some frequency select inputs; and radio frequency (RF) signal generating means coupled to the output of said numerically controlled oscillator for utilizing signals thereon to generate a digital signal having a generally 50% duty-cycle and the same selected frequency as the output signal of said nuemrically controlled oscillator.

Claim 3

Apparatus as claimed in claim 1 wherein the signal generating means includes a driver and delay means connected to produce a continuous output signal and coupled to the output of said numerically controlled oscillator for utilizing output signals thereon to produce a transition in the continuous output signal at the correct time to generate the generally 50% duty cycle and selected frequency.

Claim 4

Apparatus as claimed in claim 2 wherein the delay means includes a tapped delay line.

Claim 5

Apparatus as claimed in claim 2 wherein the signal generating means further includes memory means having predetermined delay patterns stored therein, said memory means being coupled to the frequency select input for selecting a predetermined delay pattern for each different selected frequency, being coupled to the output of the numerically controlled oscillator for selecting the specific delays in the selected delay pattern, and being coupled to the driver initiating the transitions.

Claim 6

Apparatus as claimed in claim 4 wherein the memory means is coupled to the output of the numerically controlled oscillator and to the driver by a multiplexer.

Claim 7

Apparatus as claimed in claim 5 wherein the multiplex is coupled to the driver by a clocked register.

Claim 8

Low spurious numerically controlled oscillator apparatus comprising: adding means having a first plurality of inputs adapted to receive a frequency select digital input signal; a second plurality of inputs and a plurality of outputs; a digital register having a plurality of inputs coupled to the plurality of outputs of said adding means and a plurality of outputs coupled to the second plurality of inputs of said adding means, and said digital register further having an input adapted to receive clock pulses thereon; and radio frequency (RF) digital signal generating means coupled to at least a most significant one of the plurality of outputs of said digital register for utilizing digital signals thereon at a selected frequency defined by a frequency select digital input signal on the first plurality of inputs of said adding means to generate a digital output signal having a generally 50% duty cycle and the same selected frequency as the selected frequency of the utilized digital signals.

Claim 9

Low spurious numerically controlled oscillator apparatus comprising: adding means having a first plurality of inputs adapted to receive a frequency select digital input signal; a second plurality of inputs and a plurality of outputs; a digital register having a plurality of inputs coupled to the plurality of outputs of said adding means and a plurality of outputs coupled to the second plurality of inputs of said adding means, and said digital register further having an input adapted to receive clock pulses thereon; and radio frequency (RF) digital signal generating means coupled to at least a most significant one of the plurality of outputs of said digital register for utilizing digital signals thereon at a selected frequency defined by a frequency select digital input signal on the first plurality of inputs of said adding means to generate a digital output signal having a generally 50% duty cycle and the same selected frequency as the selected frequency of the utilized digital signals.