US4635230A
Expired / Lapsed
US
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Emitter coupled logic bipolar memory cell
Assignee: Lattice Semiconductor Corp
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Filing: 1984-12-18
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Granted: 1987-01-06
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Expires: 2004-12-18
Abstract
Abstract An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to couple the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.
Inventors
- 👤 Mammen Thomas
- 👤 Wen C. Ko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:19
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/012; H10D64/0121; H10B; H10B10/00; H10B10/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
169 words
An improved ECL bipolar memory cell having a first Schottky diode, formed from a portion of a polysilicon layer and a metal silicide connected between a bit line and the collector of a first transistor; a second Schottky diode also formed from a portion of the same polysilicon layer and a metal silicide connected between a second bit line and the collector of a second transistor; said first transistor having its base connected to said collector of said second transistor, said second transistor having its base connected to the collector of said first transistor whereby a flip-flop circuit is formed; and said first and second transistors having their collectors respectively coupled to a first word line through a polysilicon load device also formed from portions of said polysilicon layer and their emitters connected together in a buried layer which is connected to a second word line to reduce alpha strike-induced errors; said cell having enhanced resistance to latch-up because of the low minority carrier efficiency of said Schottky diodes.
Claim 2
Dependent Claim
169 words
An improved ECL bipolar memory cell having a first Schottky diode, formed from a portion of a polysilicon layer and a metal silicide connected between a bit line and the collector of a first transistor; a second Schottky diode also formed from a portion of the same polysilicon layer and a metal silicide connected between a second bit line and the collector of a second transistor; said first transistor having its base connected to said collector of said second transistor, said second transistor having its base connected to the collector of said first transistor whereby a flip-flop circuit is formed; and said first and second transistors having their collectors respectively coupled to a first word line through a polysilicon load device also formed from portions of said polysilicon layer and their emitters connected together in a buried layer which is connected to a second word line to reduce alpha strike-induced errors; said cell having enhanced resistance to latch-up because of the low minority carrier efficiency of said Schottky diodes.
Claim 3
Dependent Claim
48 words
The memory cell of claim 1 wherein said metal silicide is formed by reacting with said polysilicon a metal capable of reacting to form said metal silicide selected from the class consisting of cobalt, chromium, hafnium, iridium, manganese, molybdenum, nickel, palladium, platinum, rhenium, tantalum, titanium, tungsten, and zirconium.
Claim 4
Dependent Claim
16 words
The memory cell of claim 2 wherein said metal portion of said metal silicide comprises platinum.
Claim 5
Dependent Claim
40 words
The memory cell of claim 1 wherein said load devices comprises polysilicon resistors formed over isolation oxide on the edge of the cell, said polysilicon resistors comprising portions of the same polysilicon layer from which said Schottky diodes are formed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |