Patent US4635116A successfully refreshed from Google Patents.
US4635116A
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Video signal delay circuit
Assignee: Victor Company of Japan Ltd
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Filing: 1985-02-26
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Granted: 1987-01-06
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Expires: 2005-02-26
Abstract
Abstract A video signal delay circuit comprises an input horizontal transfer register supplied serially with an input composite video signal, an input vertical transfer gate, a plurality of columns of vertical transfer registers, an output vertical transfer gate, an output horizontal transfer register, a horizontal transfer clock pulse generating circuit, a vertical transfer clock pulse generating circuit and a vertical transfer gate pulse generating circuit. The vertical transfer clock pulse generating circuit generates a vertical transfer clock pulse at a rate of once per one horizontal scanning period of the input composite video signal and additionally generates one or more vertical transfer clock pulses during a specific time period. Or, the horizontal transfer clock pulse generating circuit generates a horizontal transfer clock pulse having a selected phase or a selected number of horizontal transfer clock pulses.
Inventors
- 👤 Akira Hirota
- 👤 Takuya Tsushima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:45
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; G; G11; G11C; G11C27/00; G11C27/04
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
495 words
A video signal delay circuit comprising: an input horizontal transfer register serially supplied with an input composite video signal for transferring horizontally every time an input horizontal transfer clock pulse is applied thereto sampled signals obtained by sampling the input composite video signal by the input horizontal transfer clock pulse; an input vertical transfer gate supplied in parallel with the sampled signals from said input horizontal transfer register, for passing the sampled signals during a time period in which said input horizontal transfer register does not perform a horizontal transfer; a plurality of columns of vertical transfer registers supplied with the sampled signals from said input vertical transfer gate, each of said columns of vertical transfer registers having a constant number of stages and successively transferring vertically one of said sampled signals supplied thereto every time a vertical transfer clock pulse is applied thereto; an output vertical transfer gate for gating parallel output signals of said columns of vertical transfer registers; an output horizontal transfer register for temporarily storing said parallel output signals of said output vertical transfer gate and for transferring horizontally the stored signals every time an output horizontal transfer clock pulse is applied thereto so as to serially produce a delayed composite video signal; a horizontal transfer clock pulse generating circuit for generating the input and output horizontal transfer clock pulses based on a horizontal synchronizing signal within the input composite video signal and for supplying the input and output horizontal transfer clock pulses to said input and output horizontal transfer registers; a vertical transfer clock pulse generating circuit for generating the vertical transfer clock pulse based on horizontal and vertical synchronizing signals within the input composite video signal, said output horizontal transfer register producing a composite video signal delayed by M horizontal scanning periods when said vertical transfer clock pulse generating circuit supplies the vertical transfer clock pulse to said vertical transfer registers at a rate of once per one horizontal scanning period of the input composite video signal, where M is a natural number greater than one, said output horizontal transfer register producing a composite video signal delayed by N horizontal scanning periods when said vertical transfer clock pulse generating circuit supplies the vertical transfer clock pulse to said vertical transfer registers at a rate of once per one horizontal scanning period of the input composite video signal and one or more times at specific positions within said N horizontal scanning periods, where N is a natural number less than M; and a vertical transfer gate pulse generating circuit for generating input and output vertical transfer gate pulses which are in phase synchronism with the output vertical transfer clock pulse of said vertical transfer clock pulse generating circuit based on the horizontal and vertical synchronizing signals within the input composite video signal and for supplying the input vertical transfer gate pulse to said input vertical transfer gate and the output vertical transfer gate pulse to said output vertical transfer gate.
Claim 2
Dependent Claim
495 words
A video signal delay circuit comprising: an input horizontal transfer register serially supplied with an input composite video signal for transferring horizontally every time an input horizontal transfer clock pulse is applied thereto sampled signals obtained by sampling the input composite video signal by the input horizontal transfer clock pulse; an input vertical transfer gate supplied in parallel with the sampled signals from said input horizontal transfer register, for passing the sampled signals during a time period in which said input horizontal transfer register does not perform a horizontal transfer; a plurality of columns of vertical transfer registers supplied with the sampled signals from said input vertical transfer gate, each of said columns of vertical transfer registers having a constant number of stages and successively transferring vertically one of said sampled signals supplied thereto every time a vertical transfer clock pulse is applied thereto; an output vertical transfer gate for gating parallel output signals of said columns of vertical transfer registers; an output horizontal transfer register for temporarily storing said parallel output signals of said output vertical transfer gate and for transferring horizontally the stored signals every time an output horizontal transfer clock pulse is applied thereto so as to serially produce a delayed composite video signal; a horizontal transfer clock pulse generating circuit for generating the input and output horizontal transfer clock pulses based on a horizontal synchronizing signal within the input composite video signal and for supplying the input and output horizontal transfer clock pulses to said input and output horizontal transfer registers; a vertical transfer clock pulse generating circuit for generating the vertical transfer clock pulse based on horizontal and vertical synchronizing signals within the input composite video signal, said output horizontal transfer register producing a composite video signal delayed by M horizontal scanning periods when said vertical transfer clock pulse generating circuit supplies the vertical transfer clock pulse to said vertical transfer registers at a rate of once per one horizontal scanning period of the input composite video signal, where M is a natural number greater than one, said output horizontal transfer register producing a composite video signal delayed by N horizontal scanning periods when said vertical transfer clock pulse generating circuit supplies the vertical transfer clock pulse to said vertical transfer registers at a rate of once per one horizontal scanning period of the input composite video signal and one or more times at specific positions within said N horizontal scanning periods, where N is a natural number less than M; and a vertical transfer gate pulse generating circuit for generating input and output vertical transfer gate pulses which are in phase synchronism with the output vertical transfer clock pulse of said vertical transfer clock pulse generating circuit based on the horizontal and vertical synchronizing signals within the input composite video signal and for supplying the input vertical transfer gate pulse to said input vertical transfer gate and the output vertical transfer gate pulse to said output vertical transfer gate.
Claim 3
Dependent Claim
59 words
A video signal delay circuit as claimed in claim 1 in which said vertical transfer clock pulse generating circuit further generates the vertical transfer clock pulse (M-N) times within a vertical blanking period of the input composite video signal when a delay time of said N horizontal scanning periods is to be obtained by said video signal delay circuit.
Claim 4
Dependent Claim
114 words
A video signal delay circuit as claimed in claim 1 in which M is equal to a number of horizontal scanning lines included within one field of the input composite video signal plus one half the horizontal scanning period, N is equal to a number of horizontal scanning lines included within one field of the input composite video signal minus one half the horizontal scanning period, and said vertical transfer clock pulse generating circuit generates the vertical transfer clock pulse so that a delay time of said video signal delay circuit is alternately switched between a delay time of said M horizontal scanning periods and a delay time of said N horizontal scanning periods.
Claim 5
Dependent Claim
129 words
A video signal delay circuit as claimed in claim 2 in which N is equal to a first value N 1 or a second value N 2 , said first value N 1 being equal to one field of the input composite video signal plus one half the horizontal scanning period, said second value N 2 being equal to one field of the input composite video signal minus one half the horizontal scanning period, and said vertical transfer clock pulse generating circuit generates the vertical transfer clock pulse so that the delay time of said video signal delay circuit is alternately switched between a delay time of N 1 horizontal scanning periods and a delay time of N 2 horizontal scanning periods for every time period of one field.
Claim 6
Dependent Claim
116 words
A video signal delay circuit as claimed in claim 1 in which said vertical transfer clock pulse generating circuit generates the vertical transfer clock pulse at a rate of once per one horizontal scanning period of the input composite video signal during (2N-M) horizontal scanning periods out of the N horizontal scanning periods of the input composite video signal and generates the vertical transfer clock pulse at a rate of twice per one horizontal scanning period during the remaining (M-N) horizontal scanning periods when a delay time of said N horizontal scanning periods is to be obtained by said video signal delay circuit, where N is a natural number less than M and greater than M/2.
Claim 7
Dependent Claim
121 words
A video signal delay circuit as claimed in claim 5 in which M is equal to a number of horizontal scanning lines included within one field of the input composite video signal plus one half the horizontal scanning period, N is equal to a number of horizontal scanning lines included within one field of the input composite video signal minus one half the horizontal scanning period, and said vertical transfer clock pulse generating circuit generates the vertical transfer clock pulse so that a delay time of said video signal delay circuit is alternately switched between a delay time of said M horizontal scanning periods and a delay time of said N horizontal scanning periods for every time period of one field.
Claim 8
Dependent Claim
145 words
A video signal delay circuit as claimed in claim 5 in which N is equal to a first value N 1 or a second value N 2 , said first value N 1 being equal to a number of horizontal scanning lines included within one field of the input composite video signal plus one half the horizontal scanning period, said second value N 2 being equal to a number of horizontal scanning lines included within one field of the input composite video signal minus one half the horizontal scanning period, and said vertical transfer clock pulse generating circuit generates the vertical transfer clock pulse so that the delay time of said video signal delay circuit is alternately switched between a delay time of N 1 horizontal scanning periods and a delay time of N 2 horizontal scanning periods for every time period of one field.
Claim 9
Dependent Claim
90 words
A video signal delay circuit as claimed in claim 1 which further comprises switching circuit means having a first terminal applied with the output signal of said output horizontal transfer register and a second terminal applied with a constant voltage or the input composite video signal, said switching circuit means normally selectively passing the output signal of said output horizontal transfer register, said switching circuit means selectively passing the constant voltage or the input composite video signal at least during a time period in which a vertical transfer is performed.
Claim 10
Dependent Claim
94 words
A video signal delay circuit as claimed in claim 8 in which said switching circuit means selectively passes the constant voltage or the input composite video signal during a time period in which there is a signal lack in the output delayed composite video signal of said output horizontal transfer register which signal lack occurs at a rate of once per time period of two fields when a delayed composite video signal having a delay time thereof alternately switched for every time period of one field is obtained from said output horizontal transfer register.
Claim 11
Dependent Claim
131 words
A video signal delay circuit as claimed in claim 1 in which said horizontal transfer clock pulse generating circuit comprises oscillator means for producing pulses having a repetition frequency related to the frequency of the horizontal transfer clock pulses, said oscillator means being forcibly reset by the horizontal synchronizing signal within the input composite video signal, and gate circuit means supplied with the output pulses of said oscillator means and the horizontal synchronizing signal within the input composite video signal for producing pulses having a repetition frequency identical to that of the horizontal transfer clock pulses and having a phase which is inverted for every one horizontal scanning period of the input composite video signal, the output pulses of said gate circuit means being produced as the horizontal transfer clock pulses.
Claim 12
Dependent Claim
448 words
A video signal delay circuit comprising: an input horizontal transfer register serially supplied with an input composite video signal for transferring horizontally every time an input horizontal transfer clock pulse is applied thereto sampled signals obtained by sampling the input composite video signal by the input horizontal transfer clock pulse; an input vertical transfer gate supplied in parallel with the sampled signals from said input horizontal transfer register, for passing the sampled signals during a time period in which said input horizontal transfer register does not perform a horizontal transfer; a plurality of columns of vertical transfer registers supplied with the sampled signals from said input vertical transfer gate, each of said columns of vertical transfer registers having a constant number of stages and successively transferring vertically one of said sampled signals supplied thereto every time a vertical transfer clock pulse is applied thereto; an output vertical transfer gate for gating parallel output signals of said columns of vertical transfer registers; an output horizontal transfer register for temporarily storing said parallel output signals of said output vertical transfer gate and for transferring horizontally the stored signals every time an output horizontal transfer clock pulse is applied thereto so as to serially produce a delayed composite video signal; input and output horizontal transfer clock pulse generating circuits for generating the input and output horizontal transfer clock pulses based on a horizontal synchronizing signal within the input composite video signal and for supplying the input and output horizontal transfer clock pulses to said input and output horizontal transfer registers; a vertical transfer clock pulse generating circuit for generating the vertical transfer clock pulse based on the horizontal synchronizing signal within the input composite video signal, said output horizontal transfer register producing a composite video signal delayed by M horizontal scanning periods when said vertical transfer clock pulse generating circuit supplies the vertical transfer clock pulse to said vertical transfer registers at a rate of once per one horizontal scanning period of the input composite video signal, where M is a natural number greater than one; and input and output vertical transfer gate pulse generating circuits for generating input and output vertical transfer gate pulses based on the horizontal synchronizing signal within the input composite video signal and for supplying the input vertical transfer gate pulse to said input vertical transfer gate and the output vertical transfer gate pulse to said output vertical transfer gate, said output horizontal transfer clock pulse generating circuit generating the output horizontal transfer clock pulse with a phase which is advanced or retarded by a time period t with respect to the input horizontal transfer clock pulse, where t is smaller than one horizontal scanning period.
Claim 13
Dependent Claim
448 words
A video signal delay circuit comprising: an input horizontal transfer register serially supplied with an input composite video signal for transferring horizontally every time an input horizontal transfer clock pulse is applied thereto sampled signals obtained by sampling the input composite video signal by the input horizontal transfer clock pulse; an input vertical transfer gate supplied in parallel with the sampled signals from said input horizontal transfer register, for passing the sampled signals during a time period in which said input horizontal transfer register does not perform a horizontal transfer; a plurality of columns of vertical transfer registers supplied with the sampled signals from said input vertical transfer gate, each of said columns of vertical transfer registers having a constant number of stages and successively transferring vertically one of said sampled signals supplied thereto every time a vertical transfer clock pulse is applied thereto; an output vertical transfer gate for gating parallel output signals of said columns of vertical transfer registers; an output horizontal transfer register for temporarily storing said parallel output signals of said output vertical transfer gate and for transferring horizontally the stored signals every time an output horizontal transfer clock pulse is applied thereto so as to serially produce a delayed composite video signal; input and output horizontal transfer clock pulse generating circuits for generating the input and output horizontal transfer clock pulses based on a horizontal synchronizing signal within the input composite video signal and for supplying the input and output horizontal transfer clock pulses to said input and output horizontal transfer registers; a vertical transfer clock pulse generating circuit for generating the vertical transfer clock pulse based on the horizontal synchronizing signal within the input composite video signal, said output horizontal transfer register producing a composite video signal delayed by M horizontal scanning periods when said vertical transfer clock pulse generating circuit supplies the vertical transfer clock pulse to said vertical transfer registers at a rate of once per one horizontal scanning period of the input composite video signal, where M is a natural number greater than one; and input and output vertical transfer gate pulse generating circuits for generating input and output vertical transfer gate pulses based on the horizontal synchronizing signal within the input composite video signal and for supplying the input vertical transfer gate pulse to said input vertical transfer gate and the output vertical transfer gate pulse to said output vertical transfer gate, said output horizontal transfer clock pulse generating circuit generating the output horizontal transfer clock pulse with a phase which is advanced or retarded by a time period t with respect to the input horizontal transfer clock pulse, where t is smaller than one horizontal scanning period.
Claim 14
Dependent Claim
44 words
A video signal delay circuit as claimed in claim 11 in which said output vertical transfer gate pulse generating circuit generates the output vertical transfer gate pulse with a phase which is advanced or retarded with respect to the input vertical transfer gate pulse.
Claim 15
Dependent Claim
90 words
A video signal delay circuit as claimed in claim 11 which further comprises switching circuit means having a first terminal applied with the output signal of said output horizontal transfer register and a second terminal applied with a constant voltage or the input composite video signal, said switching circuit means normally selectively passing the output signal of said output horizontal transfer register, said switching circuit means selectively passing the constant voltage or the input composite video signal at least during a time period in which a vertical transfer is performed.
Claim 16
Dependent Claim
444 words
A video signal delay circuit comprising: an input horizontal transfer register, having a constant number of stages, serially supplied with an input composite video signal for transferring horizontally every time an input horizontal transfer clock pulse is applied thereto sampled signals obtained by sampling the input composite video signal by the input horizontal transfer clock pulse; an input vertical transfer gate supplied in parallel with the sampled signals from said input horizontal transfer register, for passing the sampled signals during a time period in which said input horizontal transfer register does not perform a horizontal transfer; a plurality of columns of vertical transfer registers supplied with the sampled signals from said input vertical transfer gate, each of said columns of vertical transfer registers having a constant number of stages and successively transferring vertically one of said sampled signals supplied thereto every time a vertical transfer clock pulse is applied thereto; an output vertical transfer gate for gating parallel output signals of said columns of vertical transfer registers; an output horizontal transfer register, having a constant number of stages, for temporarily storing said parallel output signals of said output vertical transfer gate and for transferring horizontally the stored signals every time an output horizontal transfer clock pulse is applied thereto so as to serially produce a delayed composite video signal; a horizontal transfer clock pulse generating circuit for generating a number of clock pulses greater than the number of stages in each of said input and output horizontal transfer registers during a time period in which a vertical transfer is not performed in said vertical transfer registers based on a horizontal synchronizing signal within the input composite video signal and for supplying the clock pulses as the input and output horizontal transfer clock pulses to said input and output horizontal transfer registers; a vertical transfer clock pulse generating circuit for generating the vertical transfer clock pulse based on the horizontal synchronizing signal within the input composite video signal, said output horizontal transfer register producing a composite video signal delayed by M horizontal scanning periods when said vertical transfer clock pulse generating circuit supplies the vertical transfer clock pulse to said vertical transfer registers at a rate of once per one horizontal scanning period of the input composite video signal, where M is a natural number greater than one; and a vertical transfer gate pulse generating circuit for generating input and output vertical transfer gate pulses based on the horizontal synchronizing signal within the input composite video signal and for supplying the input vertical transfer gate pulse to said input vertical transfer gate and the output vertical transfer gate pulse to said output vertical transfer gate.
Claim 17
Dependent Claim
444 words
A video signal delay circuit comprising: an input horizontal transfer register, having a constant number of stages, serially supplied with an input composite video signal for transferring horizontally every time an input horizontal transfer clock pulse is applied thereto sampled signals obtained by sampling the input composite video signal by the input horizontal transfer clock pulse; an input vertical transfer gate supplied in parallel with the sampled signals from said input horizontal transfer register, for passing the sampled signals during a time period in which said input horizontal transfer register does not perform a horizontal transfer; a plurality of columns of vertical transfer registers supplied with the sampled signals from said input vertical transfer gate, each of said columns of vertical transfer registers having a constant number of stages and successively transferring vertically one of said sampled signals supplied thereto every time a vertical transfer clock pulse is applied thereto; an output vertical transfer gate for gating parallel output signals of said columns of vertical transfer registers; an output horizontal transfer register, having a constant number of stages, for temporarily storing said parallel output signals of said output vertical transfer gate and for transferring horizontally the stored signals every time an output horizontal transfer clock pulse is applied thereto so as to serially produce a delayed composite video signal; a horizontal transfer clock pulse generating circuit for generating a number of clock pulses greater than the number of stages in each of said input and output horizontal transfer registers during a time period in which a vertical transfer is not performed in said vertical transfer registers based on a horizontal synchronizing signal within the input composite video signal and for supplying the clock pulses as the input and output horizontal transfer clock pulses to said input and output horizontal transfer registers; a vertical transfer clock pulse generating circuit for generating the vertical transfer clock pulse based on the horizontal synchronizing signal within the input composite video signal, said output horizontal transfer register producing a composite video signal delayed by M horizontal scanning periods when said vertical transfer clock pulse generating circuit supplies the vertical transfer clock pulse to said vertical transfer registers at a rate of once per one horizontal scanning period of the input composite video signal, where M is a natural number greater than one; and a vertical transfer gate pulse generating circuit for generating input and output vertical transfer gate pulses based on the horizontal synchronizing signal within the input composite video signal and for supplying the input vertical transfer gate pulse to said input vertical transfer gate and the output vertical transfer gate pulse to said output vertical transfer gate.
Claim 18
Dependent Claim
121 words
A video signal delay circuit as claimed in claim 14 which further comprises switching circuit means having a first terminal applied with the output signal of said output horizontal transfer register and a second terminal applied with a constant voltage or the input composite video signal, said switching circuit means normally selectively passing the output signal of said output horizontal transfer register, said switching circuit means selectively passing the constant voltage or the input composite video signal during a time period in which a vertical transfer is performed and during a time period in which a number of said horizontal transfer clock pulses greater than the number of stages in each of said input and output horizontal transfer registers are generated.
Claim 19
Dependent Claim
131 words
A video signal delay circuit as claimed in claim 14 in which said horizontal transfer clock pulse generating circuit comprises oscillator means for producing pulses having a repetition frequency related to the frequency of the horizontal transfer clock pulses, said oscillator means being forcibly reset by the horizontal synchronizing signal within the input composite video signal, and gate circuit means supplied with the output pulses of said oscillator means and the horizontal synchronizing signal within the input composite video signal for producing pulses having a repetition frequency identical to that of the horizontal transfer clock pulses and having a phase which is inverted for every one horizontal scanning period of the input composite video signal, the output pulses of said gate circuit means being produced as the horizontal transfer clock pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |