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US4635115A Expired / Lapsed US ⏱️ 0.0 years remaining

Synchronous separation circuit

Assignee: Citizen Watch Co Ltd
•
Filing: 1984-11-02
•
Granted: 1987-01-06
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Expires: 2004-11-02
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Abstract

Abstract A synchronous separation circuit comprises a capacitor, one end of the capacitor serving as an input terminal for receiving a synthetic video signal, a first C-MOS inverter, an input terminal of which is connected to the other end of the capacitor, a first resistor, one end of which is connected to the other end of the capacitor, a diode, one end of which is connected to the other end of the capacitor, and a second C-MOS inverter, an input terminal of which is connected to the other end of the diode, while an output terminal of which is connected directly or through a second resistor to the input terminal of the second C-MOS inverter, wherein when the synthetic video signal has positive characteristics, a potential at the other end of the first resistor is set to a value equal to or lower than a potential at the input terminal of the second C-MOS inverter, and when the synthetic video signal has negative characteristics, the potential at the other end of the first resistor is set to a value equal to or higher than the potential at the input terminal of the second C-MOS inverter, so as to provide a direct current bias voltage.

Inventors

  • 👤 Kiyoshi Kamiya

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 21:46
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/08

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 125 words
A synchronous separation circuit for a television receiver, comprising: (a) a first capacitor, one end of which is arranged to receive a synthetic video signal; (b) a first C-MOS inverter, an input terminal of which is connected to the other end of said first capacitor and one end of a diode; (c) a first resistor, one end of which is connected to said other end of said first capacitor and the other end of which is connected to an input terminal of a second C-MOS inverter; and (d) said input terminal of said second C-MOS inverter being connected to the other end of said diode, and an output terminal of said second C-MOS inverter being connected to said input terminal of said second C-MOS inverter.
Claim 2
Dependent Claim 125 words
A synchronous separation circuit for a television receiver, comprising: (a) a first capacitor, one end of which is arranged to receive a synthetic video signal; (b) a first C-MOS inverter, an input terminal of which is connected to the other end of said first capacitor and one end of a diode; (c) a first resistor, one end of which is connected to said other end of said first capacitor and the other end of which is connected to an input terminal of a second C-MOS inverter; and (d) said input terminal of said second C-MOS inverter being connected to the other end of said diode, and an output terminal of said second C-MOS inverter being connected to said input terminal of said second C-MOS inverter.
Claim 3
Dependent Claim 68 words
The synchronous separation circuit as claimed in claim 1, wherein the cathode of said diode is connected to said other end of said first capacitor, and a potential equal to or lower than the potential at the input to said second C-MOS inverter is applied to the other end of said first resistor, whereby the synchronous signal can be separated from a synthetic video signal of positive characteristic.
Claim 4
Dependent Claim 21 words
The synchronous separation circuit as defined in claim 1, wherein a second capacitor is connected between said diode and a ground.
Claim 5
Dependent Claim 54 words
The synchronous separation circuit as claimed in claim 1, wherein an output from said first C-MOS inverter is connected through a second capacitor to an input of a third C-MOS inverter, the input to said third C-MOS inverter further being connected through a further diode and a second resistor to said second C-MOS inverter.
Claim 6
Dependent Claim 29 words
The synchronous separation circuit is claimed in claim 1, wherein said output terminal of said second C-MOS inverter is connected to said input terminal thereof via a second resistor.

References Cited (Backward Citations)

JPS5860880A Cited
JPS58186270A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-01-05 1990-07-07 1991-01-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-01-05 1994-07-07 1995-01-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-01-05 1998-07-07 1999-01-06 $7700.00 Window Closed / Lapsed

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