Digitally controlled phase locked loop system having coarse and fine locking modes

Claim 2

In a digital signal processing system including a source of sampling clock signal and a source of digital samples representing a color reference signal having a predetermined frequency and phase, a phase locked loop system including a phase detector comprising: first means responsive to said sampling clock signal and to the digital samples representing said color reference signal and switchable between first and second operational modes for generating respective first and second phase error signals at an output terminal, said first and second phase error signals being generated from the values of respective first and second predetermined numbers of said digital samples; and second means coupled to said first means and responsive to the phase error signals provided at the output terminal of said first means for switching said first means between said first and second operational modes.

Claim 3

The phase detector set forth in claim 1 wherein: said first means comprises an accumulator responsive to a control signal for summing said first predetermined number of digital samples when the control signal is in a first state and for summing said second predetermined number of digital samples when the control signal is in a second state; and said second means comprises: a source of reference level signal; and a comparator for developing said control signal, being in said first state when the signal provided by said first means is greater than said reference signal and being in said second state otherwise.

Claim 4

In a digital signal processing system including a source of sampling clock signal and a source of digital samples representing a reference signal having a predetermined frequency and phase, a phase locked loop system comprising: first means including an accumulator responsive to a control signal for summing a first predetermined number of said digital samples where the control signal is in a first state and for summing a second predetermined number of said digital samples when the control signal is in a second state; a source of reference level signal; and a comparator for developing said control signal, being in said first state when the signal provided by said first means is greater than said reference signal and being in said second state when the signal provided by said first means is less than said reference signal.

Claim 5

In a digital signal processing system including a source of sampling clock signal and a source of digital samples representing a reference signal having a predetermined frequency and phase, a phase locked loop system comprising: first means including an accumulator responsive to a control signal for summing a first predetermined number of said digital samples where the control signal is in a first state and for summing a second predetermined number of said digital samples when the control signal is in a second state; a source of reference level signal; and a comparator for developing said control signal, being in said first state when the signal provided by said first means is greater than said reference signal and being in said second state when the signal provided by said first means is less than said reference signal.

Claim 6

The phase detector set forth in claim 3 wherein said first means further includes: means responsive to said control signal for dividing said first phase error signal by said first predetermined number and for dividing said second phase error signal by said second predetermined number to provide first and second phase error signals proportional to the average value of said first and second predetermined numbers of digital samples respectively.

Claim 7

In a digital signal processing system including a source of analog color reference signal having a predetermined frequency and phase, a phase locked loop coupled to said source for developing a sampling clock signal having a frequency proportional to the frequency of said color reference signal and having a predetermined phase relationship with said color reference signal, said phase locked loop comprising: sample providing means coupled to said source and responsive to said sampling clock signal for developing digital samples having values substantially equal to A sine r, A being a real number proportional to the amplitude of said reference signal and r being an angle proportional to the instantaneous difference in phase between said color reference signal and said sampling clock signal; and a phase detector comprising: first means coupled to said sample providing means for generating a first phase error signal from a first predetermined number of said digital samples in a first operational mode and for generating a second phase error signal from a second predetermined number of said samples in a second operational mode; and second means coupled to said first means and responsive to the phase error signals provided at the output terminal of said first means for switching said first means between said first and second operational modes.

Claim 8

In a digital signal processing system including a source of analog color reference signal having a predetermined frequency and phase, a phase locked loop coupled to said source for developing a sampling clock signal having a frequency proportional to the frequency of said color reference signal and having a predetermined phase relationship with said color reference signal, said phase locked loop comprising: sample providing means coupled to said source and responsive to said sampling clock signal for developing digital samples having values substantially equal to A sine r, A being a real number proportional to the amplitude of said reference signal and r being an angle proportional to the instantaneous difference in phase between said color reference signal and said sampling clock signal; and a phase detector comprising: first means coupled to said sample providing means for generating a first phase error signal from a first predetermined number of said digital samples in a first operational mode and for generating a second phase error signal from a second predetermined number of said samples in a second operational mode; and second means coupled to said first means and responsive to the phase error signals provided at the output terminal of said first means for switching said first means between said first and second operational modes.

Claim 9

The phase detector set forth in claim 5 wherein: said first means comprises an accumulator responsive to a control signal for summing said first predetermined number of digital samples when the control signal is in a first state and for summing said second predetermined number of digital samples when the control signal is in a second state; and said second means comprises: a source of reference level signal; and a comparator for developing said control signal, being in said first state when the signal provided by said first means is greater than said reference signal and being in said second state otherwise.

Claim 10

The phase detector set forth in claim 6 wherein said first means comprises: means responsive to said control signal for dividing said first phase error signal by said first predetermined number and for dividing said second phase error signal by said second predetermined number to provide first and second phase error signals proportional to the average value of said first and second predetermined numbers of digital samples respectively.

Claim 11

In a digital video signal processing system including a source of composite video signal having a chrominance signal component which includes first and second quadrature phase related color difference signal components and a color reference burst signal component having a predetermined phase relationship with respect to said first color difference signal component, a phase locked loop for developing a sampling clock signal having a frequency proportional to the frequency of said color reference burst signal and a phase relationship with respect to said color reference burst signal substantially equal to said predetermined phase relationship, and means coupled to said source and to said phase locked loop for developing digital samples representing the value of said color reference burst signal at instants determined by said sampling clock, wherein said phase locked loop includes a phase detector comprising: first means coupled to said sample providing means and switchable between first and second operational modes for generating respective first and second phase error signals at an output terminal, said first and second phase error signals representing the values of first and second predetermined numbers of said digital samples, respectively; and second means coupled to said first means and responsive to the phase error signals provided at said output terminal for switching said first means between said first and second operational modes.

Claim 12

In a digital video signal processing system including a source of composite video signal having a chrominance signal component which includes first and second quadrature phase related color difference signal components and a color reference burst signal component having a predetermined phase relationship with respect to said first color difference signal component, a phase locked loop for developing a sampling clock signal having a frequency proportional to the frequency of said color reference burst signal and a phase relationship with respect to said color reference burst signal substantially equal to said predetermined phase relationship, and means coupled to said source and to said phase locked loop for developing digital samples representing the value of said color reference burst signal at instants determined by said sampling clock, wherein said phase locked loop includes a phase detector comprising: first means coupled to said sample providing means and switchable between first and second operational modes for generating respective first and second phase error signals at an output terminal, said first and second phase error signals representing the values of first and second predetermined numbers of said digital samples, respectively; and second means coupled to said first means and responsive to the phase error signals provided at said output terminal for switching said first means between said first and second operational modes.

Claim 13

The phase detector set forth in claim 8 wherein: said first means comprises an accumulator responsive to a control signal for summing said first predetermined number of digital samples when the control signal is in a first state and for summing said second predetermined number of digital samples when the control signal is in a second state; and said second means comprises: a source of reference level signal; and a comparator for developing said control signal being in said first state when the signal provided by said first means is greater than said reference signal and being in said second state otherwise.

Claim 14

The phase detector set forth in claim 9 wherein said first means comprises: means responsive to said control signal for dividing said first phase error signal by said first predetermined number and for dividing said second phase error signal by said second predetermined number to provide first and second phase error signals proportional to the average value of said first and second predetermined numbers of digital samples respectively.