Phase-locked loop having improved locking capabilities

Claim 2

A phase-locked loop having improved off-frequency detection, comprising: means providing an alternating input signal; oscillator means providing an output signal having a frequency and phase to be locked to the frequency and phase of said alternating input signal; means providing a first reference signal; first mixer means for mixing said output signal and said first reference signal and for producing a first mixed signal in response thereto; delay means responsive to said output signal for producing a delayed signal representative of said output signal and delayed in time; second mixer means for mixing said delay signal and said first reference signal and for producing a second mixed signal in response thereto, wherein said second mixed signal is delayed with respect to said first mixed signal; logic means for logically relating said first and said second mixed signals and for producing first and second logic signals in response thereto; flip-flop means providing a flip-flop signal in response to said first and said second logic signals with the frequency of said flip-flop signal representing the difference between the frequency of said output signal and the frequency of said first reference signal; frequency detector means responsive to said flip-flop signal for producing an error signal representative of the frequency of said flip-flop signal; threshold detector means responsive to said error signal for producing a switching signal, wherein said switching signal is in a first state when said error signal exceeds a predetermined value and in a second state when said predetermined value is not exceeded; phase detector means for detecting a phase difference between said output and said input signals, and for producing a difference signal in response thereto, said phase detector means having a narrow bandwidth; and switching means selectively connecting said difference signal and said first mixed signal to said oscillator means for controlling the frequency and phase of said variable frequency output signal, said switching means responsive to said switching signal such that when said predetermined value is exceeded said first mixed signal is input to said oscillator means, and when said predetermined value is not exceeded said difference signal is input to said oscillator means.

Claim 3

The phase-locked loop of claim 1 wherein the frequency of the first reference signal is approximately equal to the frequency of the input signal.

Claim 4

The phase-locked loop of claim 1 wherein the frequency of the first mixed signal is equal to the frequency of the output signal less the frequency of the first reference signal.

Claim 5

The phase-locked loop of claim 1 wherein the frequency of the second mixed signal is equal to the frequency of the output signal less the frequency of the first reference signal.

Claim 6

The phase-locked loop of claim 1 wherein the delay means includes an inverting buffer device.

Claim 7

The phase-locked loop of claim 1 wherein the first mixer means includes an EXCLUSIVE OR gate having a first input terminal responsive to the output signal, a second input terminal responsive to the first reference signal, and an output terminal, and wherein the logic means is responsive to said output terminal.

Claim 8

The phase-locked loop of claim 1 wherein the second mixer means includes an EXCLUSIVE OR gate having a first input terminal responsive to the output signal, a second input terminal responsive to the first reference signal, and an output terminal, and wherein the logic means is responsive to said output terminal.

Claim 9

The phase-locked loop of claim 1 including: means for producing a second reference signal, wherein the frequency of the first reference signal plus the frequency of said second reference signal is approximately equal to the frequency of the input signal; third mixer means disposed between the first mixer means and the logic means, for mixing said first mixed signal and said second reference signal and for producing a third mixed signal in response thereto, wherein the logic means is responsive to said third mixed signal; and fourth mixer means disposed between the second mixer means and the logic means for mixing the second mixed signal and said second reference signal and for producing a fourth mixed signal in response thereto, wherein the logic means is responsive to said fourth mixed signal.

Claim 10

The phase-locked loop of claim 8 wherein the third mixer means includes an EXCLUSIVE OR gate having a first input terminal responsive to the first mixed signal, a second input terminal responsive to the second reference signal, and an output terminal, and wherein the third mixed signal is produced at said output terminal, and wherein the fourth mixer means includes an EXCLUSIVE OR gate having a first input terminal responsive to the second mixed signal, a second input terminal responsive to the second reference signal, and an output terminal, and wherein the fourth mixed signal is produced at said output terminal.

Claim 11

The phase-locked loop of claim 1 wherein the logic means includes: first level detector means responsive to the first mixed signal for transforming the first mixed signal to a first square wave signal; second level detector means responsive to the second mixed signal for transforming the second mixed signal to a second square wave signal; first inverter means responsive to said first square wave signal for producing a first inverted signal; second inverter means responsive to said second square wave signal for producing a second inverted signal; first summing means for producing the first logic signal wherein the first logic signal is representative of the logical sum of said first inverted signal and said second square wave signal; second summing means for producing the second logic signal wherein the second logic signal is representative of the logical sum of said second inverted signal and said first mixed signal.

Claim 12

The phase-locked loop of claim 1 wherein the flip-flop means includes an S-R type flip-flop having an inverting set input terminal responsive to the first logic signal, and an inverting reset input terminal responsive to the second logic signal.

Claim 13

The phase-locked loop of claim 1 wherein the frequency detector means includes frequency-to-voltage converter means for producing the error signal representative of the frequency of the flip-flop signal.

Claim 14

The phase-locked loop of claim 1 wherein the threshold detector means includes a Schmitt trigger responsive to the error signal for producing the switching signal.

Claim 15

A phase-locked loop having improved off-frequency detection, comprising: means providing an alternating input signal; oscillator means providing an output signal having a frequency and phase to be locked to the frequency and phase of said alternating input signal; means providing a first reference signal; frequency divider means responsive to said first reference signal for producing a second reference signal wherein the frequency of said first reference signal plus the frequency of said second reference signal is approximately equal to the frequency of said input signal; a first EXCLUSIVE OR gate for mixing said output signal and said first reference signal and for producing a first mixed signal in response thereto, said first mixed signal having a frequency equal to the frequency of said output signal less the frequency of said first reference signal; a second EXCLUSIVE OR gate for mixing said first mixed signal and said second reference signal and for producing a second mixed signal in response thereto, said second mixed signal having a frequency equal to the frequency of said first mixed signal less the frequency of said second reference signal; delay means responsive to said output signal for producing a delayed signal representative of said output signal and delayed in time; a third EXCLUSIVE OR gate for mixing said delayed signal and said first reference signal and for producing a third mixed signal in response thereto, said third mixed signal having a frequency equal to the frequency of said delayed signal less the frequency of said first reference signal; a fourth EXCLUSIVE OR gate for mixing said third mixed signal and said second reference signal and for producing a fourth mixed signal in response thereto, said fourth mixed signal having a frequency equal to the frequency of said third mixed signal less the frequency of said second reference signal; first level detector means responsive to said second mixed signal for transforming said second mixed signal to a first square wave signal; second level detector means responsive to said fourth mixed signal for transforming said fourth mixed signal to a second square wave signal; first inverter means responsive to said first square wave signal for producing a first inverted signal; first summing means for determining the logical sum of said first inverted signal and said second square wave signal and for producing a first logic signal; second inverter means responsive to said second square wave signal for producing a second inverted signal; second summing means for determining the logical sum of said second inverted signal and said first square wave signal and for producing a second logic signal; S-R flip-flop means having an inverting set input terminal responsive to said first logic signal and an inverting reset input terminal responsive to said second logic signal for producing a flip-flop signal in response thereto, with the frequency of said flip-flop signal representing the difference between the frequency of said output signal and the sum of the frequencies of said first and said second reference signals; frequency detector means for producing an error signal in response to said flip-flop signal with said error signal representing the frequency of said flip-flop signal; a Schmitt trigger responsive to said error signal for producing a switching signal, wherein said switching signal is in a first state when said error signal exceeds a predetermined value and in a second state when said predetermined value is not exceeded; phase detector means for detecting a phase difference between said output and said input signals, and for producing a difference signal in response thereto, said phase detector means having a narrow bandwidth; and switching means selectively connecting said difference signal and said third mixed signal to said oscillator means for controlling the frequency and phase of said variable frequency output signal, said switching means responsive to said switching signal such that when said predetermined value is exceeded said third mixer means is connected to said oscillator means, and when said predetermined value is not exceeded said phase detector means is connected to said oscillator means.

Claim 16

A phase-locked loop having improved off-frequency detection, comprising: means providing an alternating input signal; oscillator means providing an output signal having a frequency and phase to be locked to the frequency and phase of said alternating input signal; means providing a first reference signal; frequency divider means responsive to said first reference signal for producing a second reference signal wherein the frequency of said first reference signal plus the frequency of said second reference signal is approximately equal to the frequency of said input signal; a first EXCLUSIVE OR gate for mixing said output signal and said first reference signal and for producing a first mixed signal in response thereto, said first mixed signal having a frequency equal to the frequency of said output signal less the frequency of said first reference signal; a second EXCLUSIVE OR gate for mixing said first mixed signal and said second reference signal and for producing a second mixed signal in response thereto, said second mixed signal having a frequency equal to the frequency of said first mixed signal less the frequency of said second reference signal; delay means responsive to said output signal for producing a delayed signal representative of said output signal and delayed in time; a third EXCLUSIVE OR gate for mixing said delayed signal and said first reference signal and for producing a third mixed signal in response thereto, said third mixed signal having a frequency equal to the frequency of said delayed signal less the frequency of said first reference signal; a fourth EXCLUSIVE OR gate for mixing said third mixed signal and said second reference signal and for producing a fourth mixed signal in response thereto, said fourth mixed signal having a frequency equal to the frequency of said third mixed signal less the frequency of said second reference signal; first level detector means responsive to said second mixed signal for transforming said second mixed signal to a first square wave signal; second level detector means responsive to said fourth mixed signal for transforming said fourth mixed signal to a second square wave signal; first inverter means responsive to said first square wave signal for producing a first inverted signal; first summing means for determining the logical sum of said first inverted signal and said second square wave signal and for producing a first logic signal; second inverter means responsive to said second square wave signal for producing a second inverted signal; second summing means for determining the logical sum of said second inverted signal and said first square wave signal and for producing a second logic signal; S-R flip-flop means having an inverting set input terminal responsive to said first logic signal and an inverting reset input terminal responsive to said second logic signal for producing a flip-flop signal in response thereto, with the frequency of said flip-flop signal representing the difference between the frequency of said output signal and the sum of the frequencies of said first and said second reference signals; frequency detector means for producing an error signal in response to said flip-flop signal with said error signal representing the frequency of said flip-flop signal; a Schmitt trigger responsive to said error signal for producing a switching signal, wherein said switching signal is in a first state when said error signal exceeds a predetermined value and in a second state when said predetermined value is not exceeded; phase detector means for detecting a phase difference between said output and said input signals, and for producing a difference signal in response thereto, said phase detector means having a narrow bandwidth; and switching means selectively connecting said difference signal and said third mixed signal to said oscillator means for controlling the frequency and phase of said variable frequency output signal, said switching means responsive to said switching signal such that when said predetermined value is exceeded said third mixer means is connected to said oscillator means, and when said predetermined value is not exceeded said phase detector means is connected to said oscillator means.