Patent US4633223A successfully refreshed from Google Patents.
US4633223A
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DC offset correction circuit utilizing switched capacitor differential integrator
Assignee: Intel Corp
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Filing: 1985-05-28
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Granted: 1986-12-30
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Expires: 2005-05-28
Abstract
Abstract An integrated circuit employing a differential integrator and switched capacitor network to provide auto-zeroing. The differential integrator utilizes a feedback circuit between its inputs and outputs. A switched capacitor network coupled to the inputs of the amplifier provides voltage division of differential reference signals which determine the amount of DC offset. The amplifier then integrates the reference signals to a predetermined time constant, wherein the average voltage of the output of the integrator is used to provide auto-correction of the DC offset. A second switched capacitor voltage divider network and a second differential integrator cascaded to the first circuit provides a second time constant for fine-tuning the auto-correction signal.
Inventors
- 👤 Daniel Senderowicz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:32
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479; H03F3/005; H03H; H03H19/00; H03H19/004; H03F2200/00; H03F2200/372
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
151 words
A circuit for automatic nulling of dc offset voltages in combination with a comparator in an analog-to-digital encoder comprising: a first capacitive voltage divider being coupled to differential reference voltages, said differential reference voltages generated from said comparator, wherein said differential reference voltages being indicative of a dc offset of a signal coupled to said encoder; a first switched capacitor differential integrator having its differential input coupled to said first capacitive voltage divider to integrate said differential reference voltages with a first long time constant; a second capacitive voltage divider coupled to differential outputs of said first integrator; and a second switched capacitor differential integrator having its differential inputs coupled to said second capacitive voltage divider to integrate said outputs of said first integrator with a second long time constant; whereby a differential signal is produced by said circuit to slowly adjust an average of said differential reference voltages to zero.
Claim 2
Dependent Claim
151 words
A circuit for automatic nulling of dc offset voltages in combination with a comparator in an analog-to-digital encoder comprising: a first capacitive voltage divider being coupled to differential reference voltages, said differential reference voltages generated from said comparator, wherein said differential reference voltages being indicative of a dc offset of a signal coupled to said encoder; a first switched capacitor differential integrator having its differential input coupled to said first capacitive voltage divider to integrate said differential reference voltages with a first long time constant; a second capacitive voltage divider coupled to differential outputs of said first integrator; and a second switched capacitor differential integrator having its differential inputs coupled to said second capacitive voltage divider to integrate said outputs of said first integrator with a second long time constant; whereby a differential signal is produced by said circuit to slowly adjust an average of said differential reference voltages to zero.
References Cited (Backward Citations)
US4210872A
Cited
US4350975A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |