Darlington transistor arrangement
Abstract
Abstract The emitter of an input transistor (T 1 ) of a Darlington transistor is connected to the base of an output transistor (T 2 ). The collector of the input transistor (T 1 ) is connected to the input of a current amplifier circuit comprising a third transistor (T 3 ) arranged as a diode and having a first resistor (R 1 ) arranged in its emitter circuit, and a fourth transistor (T 4 ) having its base is connected to that of the third transistor (T 3 ) and having a second resistor (R 2 ) arranged in the emitter circuit. The collector of the fourth transistor (T 4 ) is connected to the base of the output transistor (T 2 ). The ratio between the resistance values of the first and the second resistors (R 1 , R 2 ) is larger than the ratio between the emitter areas of the fourth and the third transistor (T 4 , T 3 ). Thus, for small currents a low and for large currents a high current gain is obtained, so that the current gain factor of the output transistor (T 2 ) which decreases for large currents is compensated for partly. Moreover, the base current of the input transistor (T 1 ) remains small in the case of large output currents.
Inventors
- 👤 Adrianus J. M. van Tuijl
Bibliographic Details
Claims Analysis
Total Claims: 5References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |