Data processing system capable of transferring single-byte and double-byte data under DMA control

Claim 1

In a data processing system having a processor and a memory connected to said processor via a system bus for storing bytes of data identified by even or odd addresses and being capable of reading or writing two bytes of data having an even and a succeeding odd address in one operation in response to receipt of the even address, an input/output adaptor connected to said system bus and at least one input/output unit for effecting DMA data transfer in a controlled manner at one byte per cycle or two bytes per cycle of the processor between said input/output unit and said memory comprising: an address counter and a byte counter connected to said system bus to receive from the processor and store an address for the memory and a byte number indicating the number of bytes of data to be transferred in a DMA operation, respectively, such that the bits of the address and the byte number are stored into stages of the address counter and byte counter by shifting the bits one bit to the right so that the least significant bit of the address and the byte number are not stored in the respective counters; buffer means connected to said address counter and said system bus for receiving the contents of said address counter and for supplying said contents along with an added bit in the least significant position to said system bus as an address which is always an even address; and DMA control means for incrementing said address counter for each processor cycle a number of times according to said byte number, whereby DMA data transfer at two bytes per cycle is effected on the basis of the even addresses applied to said system bus from said buffer means.