US4631585A — Apparatus for synchronizing the operation of a mi…

Claim 1

Independent Claim 110 words

Apparatus comprising: computing means operating in response to stored program instructions generated in timed relationship to instruction cycles occurring at a rate synchronously related to a clock signal; clock signal generating means for generating said clock signal and for controlling the phase and frequency of said clock signal in response to a control signal; a source of a reference frequency signal having a reference frequency; said computing means being programmed to generate a comparison signal each time a predetermined number of instruction cycles have occurred; and comparison means for comparing the phase and frequency of said comparison signal and said reference signal and generating said control signal in response thereto.

Claim 2

Dependent Claim 110 words

Apparatus comprising: computing means operating in response to stored program instructions generated in timed relationship to instruction cycles occurring at a rate synchronously related to a clock signal; clock signal generating means for generating said clock signal and for controlling the phase and frequency of said clock signal in response to a control signal; a source of a reference frequency signal having a reference frequency; said computing means being programmed to generate a comparison signal each time a predetermined number of instruction cycles have occurred; and comparison means for comparing the phase and frequency of said comparison signal and said reference signal and generating said control signal in response thereto.

Claim 3

Dependent Claim 46 words

The apparatus recited in claim 1, wherein: the frequency of said clock signal is nominally an integer multiple of said reference frequency; and said predetermined number of instruction cyclces is selected so that the frequency of said comparison signal is nominally equal to said reference frequency.

Claim 4

Dependent Claim 71 words

The apparatus recited in claim 1, wherein: the generation of said comparison signal is marked by a first transition from a first level to a second level and the termination of said comparison signal is marked by a second transition from said second level to said first level which occurs a number of instruction cycles approximately equal to one-half said predetermined number of instruction cycles have occurred after said first transition.

Claim 5

Dependent Claim 112 words

The apparatus recited in claim 1, wherein: said computing means comprises a microprocessor embodied in an integrated circuit; said clock signal generating means comprises an amplifying device included within said integrated circuit having an input and an output connected to respective terminals of said integrated circuit, and a frequency determining network external to said integrated circuit connected in a feedback network between said input and output of said amplifying device through said terminals; and said comparison means includes a coincidence detector for generating a pulse at a circuit point when said comparison signal and said reference signal are coincident, and filter means coupled between said circuit point and one of said terminals.

Claim 6

Dependent Claim 16 words

The apparatus recited in claim 4, wherein: said coincidence detector comprises a wired AND function gate.

Claim 7

Dependent Claim 21 words

The apparatus recited in claim 1, wherein: said source of reference frequency signals comprises a source of television horizontal rate signals.

Claim 8

Dependent Claim 152 words

In a television system, apparatus comprising: computing means operating in response to program instructions generated in timed relationship to instruction cycles occurring at a rate synchronously related to a clock signal; clock signal generating means for generating said clock signal and for controlling the phase and frequency of said clock signal in response to a control signal; a source of a television horizontal rate signal defining the rate at which horizontal scanning intervals occur; said computing means being programmed to generate a comparison signal each time a first predetermined number of instruction cycles have occurred; comparison means for comparing the phase and frequency of said comparison signal and said horizontal rate signal and generating said control signal in response thereto; and said computing means being programmed to perform a predetermined operation at a second predetermined number of instruction cycles after the generation of said comparison signals in any of said scanning intervals.

Claim 9

Dependent Claim 152 words

In a television system, apparatus comprising: computing means operating in response to program instructions generated in timed relationship to instruction cycles occurring at a rate synchronously related to a clock signal; clock signal generating means for generating said clock signal and for controlling the phase and frequency of said clock signal in response to a control signal; a source of a television horizontal rate signal defining the rate at which horizontal scanning intervals occur; said computing means being programmed to generate a comparison signal each time a first predetermined number of instruction cycles have occurred; comparison means for comparing the phase and frequency of said comparison signal and said horizontal rate signal and generating said control signal in response thereto; and said computing means being programmed to perform a predetermined operation at a second predetermined number of instruction cycles after the generation of said comparison signals in any of said scanning intervals.

Claim 10

Dependent Claim 55 words

The apparatus recited in claim 7, wherein: the frequency of said clock signal is nominally an integer multiple of the frequency of said horizontal rate signal; and,. said first predetermined number of instruction cycles is selected so that the frequency of said comparison signal is nominally equal to the frequency of said horizontal rate signal.

Claim 11

Dependent Claim 72 words

The apparatus recited in claim 7, wherein: the generation of said comparison signal is marked by a first transition from a first level to a second level and the termination of said comparison signal is marked by a second transition from said second level to said first level which occurs a number of instruction cycles approximately equal to one-half said first predetermined number of instruction cycles have occurred after said first transition.

Claim 12

Dependent Claim 52 words

The apparatus recited in claim 7, wherein: there is further provided a source of a television vertical rate signal; and said computing means is programmed to be responsive to said vertical rate signal for counting the number of times said comparison signal is generated after the occurrence of said vertical rate signal.

Claim 13

Dependent Claim 75 words

The apparatus recited in claim 10, wherein: there is further provided a source of data signals corresponding to a character; and said computing means is responsive to said data signals for generating character pulses at a rate proportional to said rate of said instruction cycles for forming slices of said character at corresponding counts of said comparison signal; and coupling means for coupling said character pulses to image display devices associated with said television system.

Claim 14

Dependent Claim 113 words

The apparatus recited in claim 7, wherein: said computing means comprises a microprocessor embodied in an integrated circuit; said clock signal generating means comprises an amplifying device included within said integrated circuit having an input and an output connected to respective terminals of said integrated circuit, and a frequency determining network external to said integrated circuit connected in a feedback network between said input and output of said amplifying device through said terminals; and said comparison means includes a coincidence detector for generating a pulse at a circuit point when said comparison signal and said horizontal rate signal are coincident, and filter means coupled between said circuit point and one of said terminals.

Claim 15

Dependent Claim 16 words

The apparatus recited in claim 12, wherein: said coincidence detector comprises a wired AND function gate.

Claim 16

Dependent Claim 194 words

Apparatus comprising: a microprocessor embodied in an integrated circuit and operating in response to programmed instructions generated in timed relationship to instruction cycles occurring at a rate synchronously related to a clock signal; clock signal generating means for generating said clock signal and for controlling the phase and frequency of said clock signal in response to a control signal, said clock signal generating means comprising an amplifying device included within said integrated circuit having an input and an output connected to first and second terminals of said integrated circuit, respectively, and a frequency determining network connected in a feedback network between said input and said output of said amplifying device through said terminals; a source of a reference frequency signal having a reference frequency; said microprocessor being programmed to generate a comparison signal at a third terminal of said integrated circuit each time a predetermined number of instruction cycles have occurred; and coincidence detector means coupled to said source and said third terminal for generating a pulse at a circuit point when said reference frequency signal and said comparison signal are coincident; and filter means coupled between said circuit point and said first terminal.

Claim 17

Dependent Claim 194 words

Apparatus comprising: a microprocessor embodied in an integrated circuit and operating in response to programmed instructions generated in timed relationship to instruction cycles occurring at a rate synchronously related to a clock signal; clock signal generating means for generating said clock signal and for controlling the phase and frequency of said clock signal in response to a control signal, said clock signal generating means comprising an amplifying device included within said integrated circuit having an input and an output connected to first and second terminals of said integrated circuit, respectively, and a frequency determining network connected in a feedback network between said input and said output of said amplifying device through said terminals; a source of a reference frequency signal having a reference frequency; said microprocessor being programmed to generate a comparison signal at a third terminal of said integrated circuit each time a predetermined number of instruction cycles have occurred; and coincidence detector means coupled to said source and said third terminal for generating a pulse at a circuit point when said reference frequency signal and said comparison signal are coincident; and filter means coupled between said circuit point and said first terminal.

Claim 18

Dependent Claim 46 words

The apparatus recited in claim 14, wherein: the frequency of said clock signal is nominally an integer multiple of said reference frequency; and said predetermined number of instruction cycles is selected so that the frequency of said comparison signal is nominally equal to said reference frequency.

Claim 19

Dependent Claim 69 words

The apparatus recited in claim 14, wherein: the generation of said comparison signal is marked by a first transition from a first level to a first level and the termination of said comparison signal is marked by a second transition from said second level to said first level which occurs a number of instruction cycles approximately equal to one-half said predetermined number of instruction cycles after said first transition.

Claim 20

Dependent Claim 13 words

The apparatus recited in claim 14, wherein: said amplifying device comprises an inverter.

Claim 21

Dependent Claim 16 words

The apparatus recited in claim 14, wherein: said coincidence detector comprises a wired AND function gate.

Claim 22

Dependent Claim 21 words

The apparatus recited in claim 14, wherein: said source of reference frequency signals comprises a source of television horizontal rate signals.

Claim 23

Dependent Claim 52 words

The apparatus recited in claim 19, wherein: there is further provided a source of a television vertical rate signal; and said computing means is programmed to be responsive to said vertical rate signal for counting the number of times said comparison signal is generated after the occurrence of said vertical rate signal.

Claim 24

Dependent Claim 57 words

The apparatus recited in claim 20, wherein: there is further provided a source of data signals corresponding to a character; and said computing means is responsive to said data signals for generating character pulse at a rate proportional to said rate of said instruction cycles for slices of said character at corresponding counts of said comparison signal.

Claim 25

Dependent Claim 189 words

In a television system for forming an image on an image display device which is scanned in lines during line scanning intervals, apparatus comprising: a microprocessor embodied in an integrated circuit and operating in response to programmed instructions generated in time relationship to instruction cycles which occur in time relationship to a clock signal; clock signal generating means for generating said clock signal and for controlling its phase and frequency in response to a control signal; a source of a television synchronization signal defining the rate at which said line scanning intervals occur; synchronization means responsive to said clock signal and to said television synchronization signal for generating said control signal so as to synchronize said clock signal and thereby said instruction cycles with said television synchronization signal; a source of data signals corresponding to a character; said microprocessor being programmed for generating character pulses at a rate proportional to that of said instruction cycles during ones of said line scanning intervals; coupling means for coupling said character pulses to said image display device, said image display device being responsive to said pulses to display slices of said character.

Claim 26

Dependent Claim 189 words

In a television system for forming an image on an image display device which is scanned in lines during line scanning intervals, apparatus comprising: a microprocessor embodied in an integrated circuit and operating in response to programmed instructions generated in time relationship to instruction cycles which occur in time relationship to a clock signal; clock signal generating means for generating said clock signal and for controlling its phase and frequency in response to a control signal; a source of a television synchronization signal defining the rate at which said line scanning intervals occur; synchronization means responsive to said clock signal and to said television synchronization signal for generating said control signal so as to synchronize said clock signal and thereby said instruction cycles with said television synchronization signal; a source of data signals corresponding to a character; said microprocessor being programmed for generating character pulses at a rate proportional to that of said instruction cycles during ones of said line scanning intervals; coupling means for coupling said character pulses to said image display device, said image display device being responsive to said pulses to display slices of said character.

Claim 27

Dependent Claim 125 words

The apparatus recited in claim 22, wherein: said synchronization means includes comparison means for comparing the phase and frequency of a comparison signal generated by said microprocessor and said television synchronization signal to generate said control signal, said microprocessor being programmed to generate said comparison signal each time a predetermined number of instruction cycles have occurred; there is further provided detection means for detecting when said television synchronization signal is improper; said microprocessor is programmed to be responsive to the detection of an improper television synchronization signal for providing a substitution synchronization signal including a pulse generated each time said predetermined number of instruction cycles have occurred; and there is further provided substitution means for substituting said substitution synchronization signal for said television synchronization signal.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1989-12-22	1990-06-23	1990-12-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1993-12-22	1994-06-23	1994-12-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1997-12-22	1998-06-23	1998-12-23	$7700.00	Window Closed / Lapsed

Apparatus for synchronizing the operation of a microprocessor with a television synchronization signal useful in generating an on-screen character display

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