US4631570A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection
Assignee: NXP USA Inc
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Filing: 1984-07-03
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Granted: 1986-12-23
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Expires: 2004-07-03
Abstract
Abstract An integrated circuit power supply interconnection technique is disclosed having a highly doped, low resistivity substrate for distribution of the integrated circuit's most positive supply voltage. The substrate functions as the most positive voltage point and accomodates devices that are normally connected directly to this most positive supply voltage. A dielectric buried layer overlies a portion of the substrate and isolates the substrate supply voltage from devices that are not connected directly to the most positive supply voltage.
Inventors
- 👤 Mark S. Birrittella
- 👤 Robert H. Reuss
- 👤 Walter C. Seelbach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:05
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1908; H10D; H10D84/00; H10D84/60; H10D84/641; H10D84/642; H10W; H10W10/00; H10W10/10; H10W10/181; H10W20/00; H10W20/40; H10W20/41; H10W20/427; Y; Y10; Y10S; Y10S148/00; Y10S148/083; Y10S148/085; Y10S257/00; Y10S257/906
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
265 words
A monolithic semiconductor integrated circuit structure, comprising: a plurality of islands, each of said islands comprising at least one semiconductor device; a substrate of a first conductivity type for coupling to a voltage supply; a first region comprising a dielectric material formed between said substrate and at least one of said plurality of islands of isolating said voltage supply from said at least one of said plurality of islands; a second region having said first conductivity type and having a first portion epitaxially grown above said first region and a second portion epitaxially grown between said substrate and another of said plurality of islands; a third region having a second conductivity type formed at a surface of said first portion of said second region; a fourth region having said first conductivity type formed at a surface of said third region, said first portion of said second region, and said third and fourth regions forming a first semiconductor device; a fifth region having said second conductivity type epitaxially grown on a surface of said second portion of said second region; a sixth region having said first conductivity type epitaxially grown on a surface of said fifth region, said second portion of said second region, and said fifth and sixth regions forming a second semiconductor device; a seventh region having said second conductivity type, formed at a surface of a third portion of said second region and adjacent to said fifth region; and an eighth region having said first conductivity type formed at a surface of said substrate and extending adjacent to said second and seventh regions.
Claim 2
Dependent Claim
265 words
A monolithic semiconductor integrated circuit structure, comprising: a plurality of islands, each of said islands comprising at least one semiconductor device; a substrate of a first conductivity type for coupling to a voltage supply; a first region comprising a dielectric material formed between said substrate and at least one of said plurality of islands of isolating said voltage supply from said at least one of said plurality of islands; a second region having said first conductivity type and having a first portion epitaxially grown above said first region and a second portion epitaxially grown between said substrate and another of said plurality of islands; a third region having a second conductivity type formed at a surface of said first portion of said second region; a fourth region having said first conductivity type formed at a surface of said third region, said first portion of said second region, and said third and fourth regions forming a first semiconductor device; a fifth region having said second conductivity type epitaxially grown on a surface of said second portion of said second region; a sixth region having said first conductivity type epitaxially grown on a surface of said fifth region, said second portion of said second region, and said fifth and sixth regions forming a second semiconductor device; a seventh region having said second conductivity type, formed at a surface of a third portion of said second region and adjacent to said fifth region; and an eighth region having said first conductivity type formed at a surface of said substrate and extending adjacent to said second and seventh regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1989-12-22 | 1990-06-23 | 1990-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-22 | 1994-06-23 | 1994-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-22 | 1998-06-23 | 1998-12-23 | $7700.00 | Window Closed / Lapsed |