US4628481A
Expired / Lapsed
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Data processing apparatus
Assignee: CAMBRIDGE PARALLEL PROCESSING Ltd
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Filing: 1984-12-06
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Granted: 1986-12-09
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Expires: 2004-12-06
Abstract
Abstract Data processing apparatus is described, comprising an array of data processing elements in rows and columns. Each element has a data register for input/output. Each column of data registers can be interconnected to form a serial shift path containing either (a) the even-numbered registers, (b) the odd-numbered registers or (c) all the registers. This allows data to be shifted out of the array, one row at a time, either from the even rows, the odd rows, or all the rows. Data can be shifted into the array in a similar way. The facility for selecting the even or odd rows is useful for handling interlaced image data.
Inventors
- 👤 Stewart F. Reddaway
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:23
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8023
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
225 words
Data processing apparatus comprising a plurality of data processing elements each of which has an associated data rgister for receiving output data from that element, each data register having an associated multiplexing circuit connected to a data input of the data register, the data processing elements and their associated data registers being logically arranged in rows and columns, wherein each column of the data registers includes: (a) a first set of connection paths each of which connects a data output of a respective one of the data registers to a first input of the multiplexing circuit associated with the next data register in the same column, and (b) a second set of connection paths, distinct from the first set of connection paths, each of the second set of connection paths connecting the data output of a respective one of the data registers to a second input of the multiplexing circuit associated with the next-but-one data register in the same column, whereby the multiplexing circuits are selectively operable to connect together either (i) the even-numbered registers in each column, (ii) the odd-numbered registers in each column, or (iii) all the registsers in each column, thereby forming a serial shift path in each column allowing data either from the even rows, the odd rows, or all the rows to be shifted out, one row at a time.
Claim 2
Dependent Claim
225 words
Data processing apparatus comprising a plurality of data processing elements each of which has an associated data rgister for receiving output data from that element, each data register having an associated multiplexing circuit connected to a data input of the data register, the data processing elements and their associated data registers being logically arranged in rows and columns, wherein each column of the data registers includes: (a) a first set of connection paths each of which connects a data output of a respective one of the data registers to a first input of the multiplexing circuit associated with the next data register in the same column, and (b) a second set of connection paths, distinct from the first set of connection paths, each of the second set of connection paths connecting the data output of a respective one of the data registers to a second input of the multiplexing circuit associated with the next-but-one data register in the same column, whereby the multiplexing circuits are selectively operable to connect together either (i) the even-numbered registers in each column, (ii) the odd-numbered registers in each column, or (iii) all the registsers in each column, thereby forming a serial shift path in each column allowing data either from the even rows, the odd rows, or all the rows to be shifted out, one row at a time.
Claim 3
Dependent Claim
47 words
Data processing apparatus according to claim 1 wherein the apparatus comprises a plurality of integrated circuit chips each of which contains a plurality of the processing elements forming a portion of at least one column of processing elements, together with their associated data registers and multiplexing circuits
Claim 4
Dependent Claim
82 words
Data processing apparatus according to claim 2 wherein, wherever two adjacent data registers in the same column lie on the same integrated circuit chip, the multiplexing circuit which interconnects them lies wholly on that same chip, and wherever two adjacent data registers in the same column lie on different integrated circuit chips, the multiplexing circuit which interconnects them comprises two separate multiplexers which lie on the respective chips, these two multiplexers being interconnected by means of a single path between the chips.
Claim 5
Dependent Claim
27 words
Data processing apparatus according to claim 1 wherein the multiplexing circuits are also operable to connect the outputs of the processing elements to their associated data registers.
Claim 6
Dependent Claim
32 words
Data processing apparatus according to claim 1, wherein the outputs of the serial shift paths formed by the data registers and the interconnection means are connected to an interlaced visual display unit.
Claim 7
Dependent Claim
34 words
Data processing apparatus according to claim 1, wherein the inputs of the serial shift paths formed by the data registers and the interconnection means are connected to the output of an image encoding device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-08 | 1990-06-09 | 1990-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-08 | 1994-06-09 | 1994-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-08 | 1998-06-09 | 1998-12-09 | $7700.00 | Window Closed / Lapsed |